{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,11]],"date-time":"2026-04-11T06:47:21Z","timestamp":1775890041046,"version":"3.50.1"},"reference-count":25,"publisher":"IEEE","license":[{"start":{"date-parts":[[2026,1,3]],"date-time":"2026-01-03T00:00:00Z","timestamp":1767398400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2026,1,3]],"date-time":"2026-01-03T00:00:00Z","timestamp":1767398400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2026,1,3]]},"DOI":"10.1109\/vlsid68508.2026.00074","type":"proceedings-article","created":{"date-parts":[[2026,3,17]],"date-time":"2026-03-17T20:19:04Z","timestamp":1773778744000},"page":"353-358","source":"Crossref","is-referenced-by-count":1,"title":["Energy and Performance Optimized Computation Offloading for Near-Memory Computing"],"prefix":"10.1109","author":[{"given":"Apratim","family":"Goswami","sequence":"first","affiliation":[{"name":"Indian Institute of Information Technology,Department of Computer Science and Engineering,Guwahati,Assam,India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Satanu","family":"Maity","sequence":"additional","affiliation":[{"name":"Indian Institute of Information Technology,Department of Computer Science and Engineering,Guwahati,Assam,India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Manojit","family":"Ghose","sequence":"additional","affiliation":[{"name":"Indian Institute of Information Technology,Department of Computer Science and Engineering,Guwahati,Assam,India"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1088\/1674-1056\/ab90e7"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/3194554.3194578"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.23919\/date58400.2024.10546698"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2025.3526201"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2025.3566929"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2025.3542361"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/2749469.2750385"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2017.54"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TETC.2022.3226132"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/MDAT.2021.3095225"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/DSD53832.2021.00048"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/2872887.2750386"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2024.3403830"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID64188.2025.00105"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ISLPED52811.2021.9502483"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/HiPC58850.2023.00019"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/3470496.3527431"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/3629524"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/CGO.2004.1281665"},{"key":"ref20","first-page":"1","article-title":"NAPEL: Near-Memory Computing Application Performance Prediction via Ensemble Learning","volume-title":"Proc. of the 56th Annu. Des. Automat. Conf. (DAC)","author":"Singh","year":"2019"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/3155287"},{"key":"ref22","volume-title":"A study on performance monitoring counters in x86-architecture","volume":"43","author":"Bandyopadhyay","year":"2004"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2009.5306797"},{"key":"ref24","volume-title":"Instruction tables: Lists of instruction latencies, throughputs, and micro-operation breakdowns for Intel, AMD, and VIA CPUs","author":"Fog","year":"2022"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/2818950.2818985"}],"event":{"name":"2026 39th International Conference on VLSI Design & 25th International Conference on Embedded Systems (VLSID)","location":"Pune, India","start":{"date-parts":[[2026,1,3]]},"end":{"date-parts":[[2026,1,7]]}},"container-title":["2026 39th International Conference on VLSI Design & 25th International Conference on Embedded Systems (VLSID)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11433189\/11433171\/11433318.pdf?arnumber=11433318","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,3,18]],"date-time":"2026-03-18T05:29:13Z","timestamp":1773811753000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11433318\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,1,3]]},"references-count":25,"URL":"https:\/\/doi.org\/10.1109\/vlsid68508.2026.00074","relation":{},"subject":[],"published":{"date-parts":[[2026,1,3]]}}}