{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,21]],"date-time":"2026-05-21T08:27:46Z","timestamp":1779352066512,"version":"3.51.4"},"reference-count":9,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2007,10]]},"DOI":"10.1109\/vlsisoc.2007.4402475","type":"proceedings-article","created":{"date-parts":[[2007,12,18]],"date-time":"2007-12-18T15:01:08Z","timestamp":1197990068000},"page":"72-77","source":"Crossref","is-referenced-by-count":2,"title":["VLSI models of network-on-chip interconnect"],"prefix":"10.1109","author":[{"given":"Dimitrios N.","family":"Serpanos","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wayne","family":"Wolf","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","author":"de micheli","year":"2006","journal-title":"Networks on Chips Technology and Tools"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ASIC.1996.551961"},{"key":"ref6","author":"weste","year":"2005","journal-title":"CMOS VLSI Design A Circuits and Systems Perspective"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1007\/b105353"},{"key":"ref8","author":"bakoglu","year":"1990","journal-title":"Circuits Interconnections and Packaging for VLSI"},{"key":"ref7","author":"baker","year":"2005","journal-title":"CMOS Circuit Design Layout and Simulation"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/76.475897"},{"key":"ref9","doi-asserted-by":"crossref","first-page":"1182","DOI":"10.1109\/DATE.2005.11","article-title":"A design flow for application-specific networks on chip with guaranteed performance to accelreate SoC design and verification","volume":"2","author":"goossens","year":"2005","journal-title":"Proceedings of the conference on Design Automation and Test in Europe"},{"key":"ref1","author":"wolf","year":"2002","journal-title":"Modern VLSI Design System-on-Chip Design"}],"event":{"name":"2007 IFIP International Conference on Very Large Scale Integration","location":"Atlanta, GA, USA","start":{"date-parts":[[2007,10,15]]},"end":{"date-parts":[[2007,10,17]]}},"container-title":["2007 IFIP International Conference on Very Large Scale Integration"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4402461\/4402462\/04402475.pdf?arnumber=4402475","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,17]],"date-time":"2017-06-17T22:17:38Z","timestamp":1497737858000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4402475\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007,10]]},"references-count":9,"URL":"https:\/\/doi.org\/10.1109\/vlsisoc.2007.4402475","relation":{},"subject":[],"published":{"date-parts":[[2007,10]]}}}