{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T15:53:56Z","timestamp":1730303636794,"version":"3.28.0"},"reference-count":14,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2007,10]]},"DOI":"10.1109\/vlsisoc.2007.4402486","type":"proceedings-article","created":{"date-parts":[[2007,12,18]],"date-time":"2007-12-18T20:01:08Z","timestamp":1198008068000},"page":"134-139","source":"Crossref","is-referenced-by-count":3,"title":["New tool support and architectures in adaptive reconfigurable computing"],"prefix":"10.1109","author":[{"given":"Juergen","family":"Becker","sequence":"first","affiliation":[]},{"given":"Adam","family":"Donlin","sequence":"additional","affiliation":[]},{"given":"Michael","family":"Huebner","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2005.63"},{"key":"ref11","article-title":"Physica12D Morphware and Power Reduction Methods for Everyone","author":"becker","year":"2006","journal-title":"Proc Dagstuhl Seminar"},{"key":"ref12","article-title":"Model and Methodology for the Synthesis of Heterogeneous and Partially Reconfigurable Systems","author":"florian","year":"2007","journal-title":"Proceedings of the Reconfigurable Architecture Workshop"},{"key":"ref13","article-title":"Exploration, Partitioning and Simulation of Reconfigurable Systems","volume":"3","author":"dittmann","year":"2007","journal-title":"it - Information Technology Journal"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2007.364642"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2004.1303106"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.1998.707895"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/SBCCI.2003.1232842"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2003.1253642"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2006.888404"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2002.998307"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4020-5869-1_22"},{"key":"ref1","first-page":"251","article-title":"JBits Design Abstractions","author":"patterson","year":"2001","journal-title":"FCCM"},{"key":"ref9","article-title":"New 2-Dimensional Partial Dynamic Reconfiguration Techniques for Real-Time Adaptive Microelectronic Circuits","author":"h\u00fcbner","year":"0","journal-title":"ISVLSI"}],"event":{"name":"2007 IFIP International Conference on Very Large Scale Integration","start":{"date-parts":[[2007,10,15]]},"location":"Atlanta, GA, USA","end":{"date-parts":[[2007,10,17]]}},"container-title":["2007 IFIP International Conference on Very Large Scale Integration"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4402461\/4402462\/04402486.pdf?arnumber=4402486","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,16]],"date-time":"2017-03-16T19:32:44Z","timestamp":1489692764000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4402486\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007,10]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/vlsisoc.2007.4402486","relation":{},"subject":[],"published":{"date-parts":[[2007,10]]}}}