{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T16:56:36Z","timestamp":1729616196996,"version":"3.28.0"},"reference-count":54,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2007,10]]},"DOI":"10.1109\/vlsisoc.2007.4402490","type":"proceedings-article","created":{"date-parts":[[2007,12,18]],"date-time":"2007-12-18T15:01:08Z","timestamp":1197990068000},"page":"157-162","source":"Crossref","is-referenced-by-count":3,"title":["Simulation of hybrid computer architectures: simulators, methodologies and recommendations"],"prefix":"10.1109","author":[{"family":"Pranav","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Jaehwan John Lee","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1145\/508352.508353"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/2.982916"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/IPPS.1997.580842"},{"key":"ref32","article-title":"Accelerating Architectural Simulation by Parallel Execution of Trace Samples","author":"lauterbach","year":"1993","journal-title":"Sun Microsystems Laboratory Technical Report TR-93–22"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1145\/244804.244808"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1016\/j.parco.2004.02.003"},{"journal-title":"SPEC CPU","year":"2000","key":"ref37"},{"journal-title":"MPI Homepage","year":"2007","key":"ref36"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1145\/128738.128740"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1145\/169627.169852"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/944645.944651"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/55595.55596"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1145\/643114.643116"},{"journal-title":"DRC Computer Corporation","year":"2007","key":"ref2"},{"journal-title":"Celoxica RCHTX System","year":"2007","key":"ref1"},{"key":"ref20","doi-asserted-by":"crossref","first-page":"92","DOI":"10.1145\/1105734.1105747","article-title":"Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset","author":"martin","year":"2005","journal-title":"SIGARCH Comput Archit News"},{"key":"ref22","first-page":"51","article-title":"Design Space Exploration of Multiprocessor Systems with Multicontext Reconfigurable coprocessors","author":"vaidya","year":"2007","journal-title":"Proceedings of the Engineering of Reconfigurable Systems and Algorithms ERSA '02"},{"key":"ref21","article-title":"VASA: A Simulator Infrastructure with Adjustable Fidelity","author":"wallin","year":"2005","journal-title":"Parallel and Distributed Computing and Systems"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2006.79"},{"year":"2007","key":"ref23"},{"journal-title":"Myricom Page for Myrinet","year":"2007","key":"ref26"},{"key":"ref25","article-title":"Wisconsin Wind Tunnel II: A Fast and Portable Parallel Architecture Simulator","author":"mukherjee","year":"1997","journal-title":"Workshop on Performance Analysis and its Impact on Design"},{"journal-title":"AMD Multicore Website","year":"2007","key":"ref50"},{"journal-title":"Intel Multicore Website","year":"2007","key":"ref51"},{"journal-title":"OpenFPGA consortium","year":"2007","key":"ref54"},{"article-title":"Communicating Sequential Processes","year":"1985","author":"hoare","key":"ref53"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2002.805829"},{"journal-title":"Performance Guidelines for AMD Athlon 64 and AMD Opteron ccNUMA Multiprocessor Systems","year":"2006","key":"ref10"},{"journal-title":"Mentor Graphics ModelSim","year":"0","key":"ref40"},{"journal-title":"Xilinx Corporation","year":"2007","key":"ref11"},{"journal-title":"Altera Corporation","year":"2007","key":"ref12"},{"journal-title":"Actel Corporation","year":"2007","key":"ref13"},{"journal-title":"Lattice Semiconductor Corporation","year":"2007","key":"ref14"},{"journal-title":"QuickLogic Corporation","year":"2007","key":"ref15"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.1996.564808"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/2.982917"},{"key":"ref18","article-title":"RSIM: An Execution-Driven Simulator for ILP-Based Shared-Memory Multiprocessors and Uniprocessors","author":"pai","year":"1997","journal-title":"Proceedings of the Third Workshop on Computer Architecture Education"},{"journal-title":"YACSIM Reference Manual Rice University version 2 1 1 edition","year":"1993","author":"jump","key":"ref19"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2006.44"},{"journal-title":"XtremeData Inc","year":"2007","key":"ref3"},{"journal-title":"IEEE Verilog Standardization Group","year":"2007","key":"ref6"},{"journal-title":"VASG VHDL Analysis and Standardization Group","year":"2007","key":"ref5"},{"journal-title":"HyperTransport consortium","year":"2007","key":"ref8"},{"key":"ref49","article-title":"Streamlt: A Language for Streaming Applications","author":"thies","year":"2002","journal-title":"Proceedings of the 2002 International Conference on Compiler Construction"},{"journal-title":"SystemC Community Website","year":"2007","key":"ref7"},{"journal-title":"NUMA HyperTransport 64-Bit Windows and You","year":"2006","key":"ref9"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1117\/12.402527"},{"article-title":"A Device-Level FPGA Simulator","year":"2004","author":"hunter","key":"ref45"},{"key":"ref48","first-page":"239","article-title":"BoardScope: a debug tool for reconfigurable systems","volume":"3526","author":"levi","year":"1998","journal-title":"Proceedings of SPIE"},{"article-title":"IHDLBits: An Open-Source Model for FPGA Design Automation","year":"2004","author":"poetter","key":"ref47"},{"journal-title":"Mentor Graphiscs Seamless FPGA","year":"2007","key":"ref42"},{"journal-title":"Mentor Graphics Hardware\/Software Co-Verification Seamless","year":"2007","key":"ref41"},{"key":"ref44","article-title":"VTsim: A Virtex-II Device Simulator","author":"hunter","year":"2004","journal-title":"Proceedings of the Engineering of Reconfigurable Systems and Algorithms ERSA '02"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2006.311212"}],"event":{"name":"2007 IFIP International Conference on Very Large Scale Integration","start":{"date-parts":[[2007,10,15]]},"location":"Atlanta, GA, USA","end":{"date-parts":[[2007,10,17]]}},"container-title":["2007 IFIP International Conference on Very Large Scale Integration"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4402461\/4402462\/04402490.pdf?arnumber=4402490","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,17]],"date-time":"2017-06-17T22:17:38Z","timestamp":1497737858000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4402490\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007,10]]},"references-count":54,"URL":"https:\/\/doi.org\/10.1109\/vlsisoc.2007.4402490","relation":{},"subject":[],"published":{"date-parts":[[2007,10]]}}}