{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T12:07:45Z","timestamp":1759147665123,"version":"3.28.0"},"reference-count":15,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2007,10]]},"DOI":"10.1109\/vlsisoc.2007.4402522","type":"proceedings-article","created":{"date-parts":[[2007,12,18]],"date-time":"2007-12-18T15:01:08Z","timestamp":1197990068000},"page":"320-323","source":"Crossref","is-referenced-by-count":16,"title":["A genetic algorithm based heuristic technique for power constrained test scheduling in core-based SOCs"],"prefix":"10.1109","author":[{"given":"Chandan","family":"Giri","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Soumojit","family":"Sarkar","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Santanu","family":"Chattopadhyay","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/1120725.1120937"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2006.871757"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-37275-2_82"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1088\/1742-6596\/48\/1\/123"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2002.1041802"},{"journal-title":"An Introduction to Genetic Algorithm","year":"0","author":"mitchell","key":"ref15"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2001.990293"},{"key":"ref3","article-title":"Test Wrapper and Test access mechanism co-optimization forsystem-on-chip","volume":"18","author":"iyengar","year":"2002","journal-title":"JETTA"},{"key":"ref6","first-page":"100","article-title":"Using a Distributed Bin-Packing Approach for Core-based SOC Test Scheduling with Power Constraints","author":"xia","year":"2003","journal-title":"Proc ICCAD"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2002.1041747"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2002.1041804"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1007\/s10836-005-2911-4"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/43.875306"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2000.894302"},{"key":"ref9","first-page":"325","article-title":"SOC Test Schdeuling Using Simulated Annealing","author":"zou","year":"2003","journal-title":"Proc VTS"}],"event":{"name":"2007 IFIP International Conference on Very Large Scale Integration","start":{"date-parts":[[2007,10,15]]},"location":"Atlanta, GA, USA","end":{"date-parts":[[2007,10,17]]}},"container-title":["2007 IFIP International Conference on Very Large Scale Integration"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4402461\/4402462\/04402522.pdf?arnumber=4402522","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,16]],"date-time":"2017-03-16T17:10:28Z","timestamp":1489684228000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4402522\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007,10]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/vlsisoc.2007.4402522","relation":{},"subject":[],"published":{"date-parts":[[2007,10]]}}}