{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T17:41:37Z","timestamp":1729618897421,"version":"3.28.0"},"reference-count":14,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010,9]]},"DOI":"10.1109\/vlsisoc.2010.5642625","type":"proceedings-article","created":{"date-parts":[[2010,11,30]],"date-time":"2010-11-30T21:36:29Z","timestamp":1291152989000},"page":"43-48","source":"Crossref","is-referenced-by-count":1,"title":["Enabling fast Network-on-Chip topology selection: an FPGA-based runtime reconfigurable prototyper"],"prefix":"10.1109","author":[{"given":"Paolo","family":"Meloni","sequence":"first","affiliation":[]},{"given":"Simone","family":"Secchi","sequence":"additional","affiliation":[]},{"given":"Luigi","family":"Raffo","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"doi-asserted-by":"publisher","key":"ref10","DOI":"10.1155\/2007\/50285"},{"doi-asserted-by":"publisher","key":"ref11","DOI":"10.1109\/MCAS.2004.1330747"},{"key":"ref12","doi-asserted-by":"crossref","first-page":"884","DOI":"10.1109\/DATE.2004.1268999","article-title":"XpipesCompiler: a Tool for Instantiating Application Specific Networks-on-Chip","volume":"2","author":"jalabert","year":"2004","journal-title":"Design Automation and Test in Europe Conference and Exhibition 2004 Proceedings"},{"doi-asserted-by":"publisher","key":"ref13","DOI":"10.1109\/NANONET.2006.346217"},{"key":"ref14","first-page":"24","article-title":"The SPLASH-2 Programs: Characterization and Methodological Considerations","volume":"0","author":"singh","year":"1995","journal-title":"Computer Architecture International Symposium on"},{"key":"ref4","first-page":"12","article-title":"Architectural Exploration of MPSoC Designs Based on an FPGA Emulation Framework","author":"del valle","year":"2006","journal-title":"XXII Conference on Design of Circuits and Integrated Systems (DCIS)"},{"key":"ref3","article-title":"RAMP: A Research Accelerator for Multiple Processors","author":"wawrzynek","year":"2006","journal-title":"Tech Rep UCB\/EECS-2006&#x2013;76"},{"doi-asserted-by":"publisher","key":"ref6","DOI":"10.1109\/MICRO.2007.36"},{"doi-asserted-by":"publisher","key":"ref5","DOI":"10.1109\/ISCAS.2005.1465100"},{"doi-asserted-by":"publisher","key":"ref8","DOI":"10.1109\/ReConFig.2008.74"},{"key":"ref7","doi-asserted-by":"crossref","first-page":"58","DOI":"10.1109\/RSP.2008.31","article-title":"An automated design flow for NoCbased MPSoCs on FPGA","author":"lukovic","year":"2008","journal-title":"RSP '08 Proceedings of the 2008 the 19th IEEE\/IFIP International Symposium on Rapid System Prototyping"},{"year":"0","author":"ramirez","journal-title":"CellSim Modular Simulator for Heterogeneous Multiprocessor Architectures","key":"ref2"},{"doi-asserted-by":"publisher","key":"ref1","DOI":"10.1007\/s11265-005-6648-1"},{"doi-asserted-by":"publisher","key":"ref9","DOI":"10.1109\/LES.2010.2044365"}],"event":{"name":"2010 18th IEEE\/IFIP International Conference on VLSI and System-on-Chip (VLSI-SoC)","start":{"date-parts":[[2010,9,27]]},"location":"Madrid, Spain","end":{"date-parts":[[2010,9,29]]}},"container-title":["2010 18th IEEE\/IFIP International Conference on VLSI and System-on-Chip"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5629484\/5642591\/05642625.pdf?arnumber=5642625","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,19]],"date-time":"2017-06-19T16:42:39Z","timestamp":1497890559000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5642625\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,9]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/vlsisoc.2010.5642625","relation":{},"subject":[],"published":{"date-parts":[[2010,9]]}}}