{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T15:41:50Z","timestamp":1730302910520,"version":"3.28.0"},"reference-count":22,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010,9]]},"DOI":"10.1109\/vlsisoc.2010.5642690","type":"proceedings-article","created":{"date-parts":[[2010,11,30]],"date-time":"2010-11-30T21:36:29Z","timestamp":1291152989000},"page":"375-380","source":"Crossref","is-referenced-by-count":6,"title":["Characterization of chip-to-chip wireless interconnections based on capacitive coupling"],"prefix":"10.1109","author":[{"given":"R.","family":"Cardu","sequence":"first","affiliation":[]},{"given":"E.","family":"Franchi","sequence":"additional","affiliation":[]},{"given":"R.","family":"Guerrieri","sequence":"additional","affiliation":[]},{"given":"M.","family":"Scandiuzzo","sequence":"additional","affiliation":[]},{"given":"S.","family":"Cani","sequence":"additional","affiliation":[]},{"given":"L.","family":"Perugini","sequence":"additional","affiliation":[]},{"given":"S.","family":"Spolzino","sequence":"additional","affiliation":[]},{"given":"R.","family":"Canegallo","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2005.136"},{"key":"ref11","first-page":"4142","article-title":"A Capacitive Coupling of Data And Power for 3D Silicon-on-Insulator VLSI","volume":"4","author":"andreou","year":"0","journal-title":"ISCAS'05"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1016\/j.mee.2006.10.052"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.859881"},{"key":"ref14","first-page":"356","article-title":"3D Capacitive Interconnections with Mono- and Bi-Directional Capabilities","author":"fazzi","year":"0","journal-title":"ISSCC'07"},{"journal-title":"Comsol Multyphysics","year":"0","key":"ref15"},{"journal-title":"Synopsys® Star-RCXT™ software","year":"0","key":"ref16"},{"journal-title":"Synopsys® Raphael NXT™ software","year":"0","key":"ref17"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/22.216475"},{"key":"ref19","article-title":"Yield prediction for 3D capacitive interconnections","author":"fazzi","year":"0","journal-title":"ICCAD '06"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1016\/j.mee.2005.07.052"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/DTIP.2008.4752966"},{"key":"ref6","first-page":"991","article-title":"A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy","author":"loi","year":"0","journal-title":"ACM Design Automation Conference"},{"key":"ref5","first-page":"1","article-title":"3D system integration technologies","author":"ramm","year":"0","journal-title":"ICIC'07"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1093\/ietele\/e90-c.4.829"},{"key":"ref7","first-page":"97","article-title":"A 65 fJ\/b inductive-coupling inter-chip transceiver using charge recycling technique for power-aware 3D system integration","author":"niitsu","year":"0","journal-title":"ASSCC 2008"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC.2008.4550074"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2004.1332633"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2003.1249442"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2009.5280782"},{"key":"ref22","article-title":"3D Assembly Technology for Hybrid Integration of Heterogenous Devices","author":"jung","year":"0","journal-title":"DTIP 2006 26–28"},{"journal-title":"NorChip","article-title":"Modeling capacitive links for broadband inter-chip communication","year":"2007","key":"ref21"}],"event":{"name":"2010 18th IEEE\/IFIP International Conference on VLSI and System-on-Chip (VLSI-SoC)","start":{"date-parts":[[2010,9,27]]},"location":"Madrid, Spain","end":{"date-parts":[[2010,9,29]]}},"container-title":["2010 18th IEEE\/IFIP International Conference on VLSI and System-on-Chip"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5629484\/5642591\/05642690.pdf?arnumber=5642690","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T11:10:28Z","timestamp":1490094628000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5642690\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,9]]},"references-count":22,"URL":"https:\/\/doi.org\/10.1109\/vlsisoc.2010.5642690","relation":{},"subject":[],"published":{"date-parts":[[2010,9]]}}}