{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T13:51:50Z","timestamp":1725457910969},"reference-count":16,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010,9]]},"DOI":"10.1109\/vlsisoc.2010.5642694","type":"proceedings-article","created":{"date-parts":[[2010,11,30]],"date-time":"2010-11-30T21:36:29Z","timestamp":1291152989000},"page":"396-401","source":"Crossref","is-referenced-by-count":2,"title":["Fully adaptive multicore architectures through statically-directed dynamic execution reconfigurations"],"prefix":"10.1109","author":[{"given":"Chengmo","family":"Yang","sequence":"first","affiliation":[]},{"given":"Alex","family":"Orailoglu","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"doi-asserted-by":"publisher","key":"ref10","DOI":"10.1109\/TPDS.2002.1011417"},{"doi-asserted-by":"publisher","key":"ref11","DOI":"10.1145\/1120725.1120793"},{"doi-asserted-by":"publisher","key":"ref12","DOI":"10.1109\/40.16792"},{"key":"ref13","doi-asserted-by":"crossref","first-page":"130","DOI":"10.1109\/ICPADS.1998.741030","article-title":"The XBW model for dependable real-time systems","author":"chaesson","year":"1998","journal-title":"Proc Int l Conf Parallel and Distributed Systems"},{"key":"ref14","first-page":"63","article-title":"Towards No-cost Adaptive MPSoC Static Schedules through Exploitation of Logical-to-physical Core Mapping Latitude","author":"yang","year":"2009","journal-title":"DATE'09"},{"doi-asserted-by":"publisher","key":"ref15","DOI":"10.1109\/71.503776"},{"doi-asserted-by":"publisher","key":"ref16","DOI":"10.1109\/HSC.1998.666245"},{"key":"ref4","first-page":"31","article-title":"Experimental Fault Analysis of 1Mb SRAM Chips","author":"goto","year":"1997","journal-title":"VLSI Test Symposium"},{"doi-asserted-by":"publisher","key":"ref3","DOI":"10.1109\/DSN.2004.1311888"},{"year":"0","journal-title":"International Technology Roadmap for Semiconductors (ITRS)","article-title":"ITRS 2009 Edition: System Drivers","key":"ref6"},{"key":"ref5","article-title":"Thermal Performance Challenges from Silicon to Systems","author":"viswanath","year":"2000","journal-title":"Intel Technology Journal"},{"doi-asserted-by":"publisher","key":"ref8","DOI":"10.1145\/1346281.1346314"},{"doi-asserted-by":"publisher","key":"ref7","DOI":"10.1145\/1289816.1289824"},{"doi-asserted-by":"publisher","key":"ref2","DOI":"10.1016\/S0026-2714(03)00183-5"},{"doi-asserted-by":"publisher","key":"ref1","DOI":"10.1007\/s10825-004-7038-9"},{"doi-asserted-by":"publisher","key":"ref9","DOI":"10.1109\/IPDPS.2008.4536297"}],"event":{"name":"2010 18th IEEE\/IFIP International Conference on VLSI and System-on-Chip (VLSI-SoC)","start":{"date-parts":[[2010,9,27]]},"location":"Madrid, Spain","end":{"date-parts":[[2010,9,29]]}},"container-title":["2010 18th IEEE\/IFIP International Conference on VLSI and System-on-Chip"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5629484\/5642591\/05642694.pdf?arnumber=5642694","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,6,6]],"date-time":"2019-06-06T17:58:51Z","timestamp":1559843931000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5642694\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,9]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1109\/vlsisoc.2010.5642694","relation":{},"subject":[],"published":{"date-parts":[[2010,9]]}}}