{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T15:37:08Z","timestamp":1729611428297,"version":"3.28.0"},"reference-count":34,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,10]]},"DOI":"10.1109\/vlsisoc.2011.6081634","type":"proceedings-article","created":{"date-parts":[[2011,11,21]],"date-time":"2011-11-21T21:42:27Z","timestamp":1321911747000},"page":"130-135","source":"Crossref","is-referenced-by-count":0,"title":["Exploiting maximum throughput in 3D multicore architectures with stacked NUCA cache"],"prefix":"10.1109","author":[{"given":"Asim","family":"Khan","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kyungsu","family":"Kang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Chong-Min Kyung","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"journal-title":"Intel Homepage","year":"2008","key":"ref33"},{"key":"ref32","article-title":"CACTI 4.0","author":"tarjan","year":"2006","journal-title":"HP Laboratories Palo Alto CA Tech Rep HPL-2006–86"},{"key":"ref31","first-page":"313","article-title":"Cache miss behavior: is it $\\surd{}2$?","author":"hartstein","year":"0","journal-title":"Proceedings of the 3rd conference on Computing frontiers (CF ‘06)"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1145\/1594233.1594306"},{"key":"ref34","first-page":"1042","article-title":"Temperature and supply voltage aware performance and power modeling at microarchitecture level","volume":"24","author":"liao","year":"2005","journal-title":"IEEE TCAD"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/1283780.1283826"},{"key":"ref11","first-page":"105","article-title":"Scheduling threads for constructive cache sharing on CMPs","author":"chen","year":"0","journal-title":"Proceedings of the nineteenth annual ACM symposium on Parallel algorithms and architectures (SPAA ‘07)"},{"key":"ref12","first-page":"852","article-title":"Dynamic thread and data mapping for NoC based CMPs","year":"0","journal-title":"Proceedings of the 46th Annual Design Automation Conference(DAC ‘09)"},{"key":"ref13","doi-asserted-by":"crossref","first-page":"1479","DOI":"10.1109\/TCAD.2008.925793","article-title":"Three-dimensional chip-multiprocessor runtime thermal management","volume":"27","author":"zhu","year":"2008","journal-title":"IEEE Trans Comput-Aided Design Integr Circuits Syst"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2009.27"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/1289816.1289846"},{"key":"ref16","article-title":"Optimal topology exploration for application-specific 3D architectures","author":"ozturk","year":"0","journal-title":"Proceedings of the 2006 Asia and South Pacific Design Automation Conference (ASP-DAC ‘06)"},{"key":"ref17","first-page":"1361","article-title":"Thermal-aware memory mapping in 3D design","author":"hsieh","year":"2009","journal-title":"Proc DATE"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/1594233.1594306"},{"key":"ref19","first-page":"34","article-title":"The ALPBench benchmark suite for complex multimedia applications","author":"li","year":"2005","journal-title":"Proc Int Symp Workload Characterization"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2011.5770786"},{"key":"ref4","first-page":"111","article-title":"Fair cache sharing and partitioning in a chip multiprocessor architecture","author":"kim","year":"0","journal-title":"Proc PACT 2004 IEEE Computer Society"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.49"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2059290"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/980152.980157"},{"key":"ref29","doi-asserted-by":"crossref","first-page":"130","DOI":"10.1145\/1150019.1136497","article-title":"Design and Management of 3D Chip Multiprocessors Using Network-in-Memory","volume":"34","author":"li","year":"2006","journal-title":"SIGARCH Comput Archit News"},{"key":"ref5","article-title":"CACTI 4.0","author":"tarjan","year":"2006","journal-title":"HP Laboratories Palo Alto CA Tech Rep HPL-2006–86"},{"journal-title":"Standard Performance Evaluation Corporation","year":"0","key":"ref8"},{"key":"ref7","article-title":"Temptor: A lightweight runtime temperature monitoring tool using performance counters","author":"han","year":"2006","journal-title":"Proc 3rd Workshop on TCAS Held in conjunction with ISCA-33"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/635506.605420"},{"journal-title":"Free Computational Fluid Dynamics","year":"0","key":"ref9"},{"journal-title":"Intel Products","year":"0","key":"ref1"},{"key":"ref20","first-page":"106","article-title":"The implementation of 65nm dual-core 64b Merom processor","author":"sakran","year":"2007","journal-title":"Proc ISSCC"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.850860"},{"key":"ref21","first-page":"991","article-title":"A Thermally-Aware Performance Analysis of Vertically Integrated (3-D) Processor-Memory Hierarchy","author":"loi","year":"2006","journal-title":"Proceedings of the 43rd Annual Design Automation Conference DAC"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS.2011.6026350"},{"journal-title":"Intel core2 duo processors and Intel core2 extreme processors for platforms based on mobile Intel 965 express chipset family","year":"2008","key":"ref23"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2008.15"},{"key":"ref25","doi-asserted-by":"crossref","first-page":"29","DOI":"10.1109\/JSSC.2007.910957","article-title":"An 80-tile sub-100-W TeraFLOPS processor in 65-nm CMOS","volume":"43","author":"sand","year":"2008","journal-title":"IEEE Journalof Solid State Circuits"}],"event":{"name":"2011 IEEE\/IFIP 19th International Conference on VLSI and System-on-Chip (VLSI-SoC)","start":{"date-parts":[[2011,10,3]]},"location":"Kowloon, Hong Kong","end":{"date-parts":[[2011,10,5]]}},"container-title":["2011 IEEE\/IFIP 19th International Conference on VLSI and System-on-Chip"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6069623\/6081592\/06081634.pdf?arnumber=6081634","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,20]],"date-time":"2017-06-20T10:06:56Z","timestamp":1497953216000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6081634\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,10]]},"references-count":34,"URL":"https:\/\/doi.org\/10.1109\/vlsisoc.2011.6081634","relation":{},"subject":[],"published":{"date-parts":[[2011,10]]}}}