{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T11:55:45Z","timestamp":1759146945033},"reference-count":14,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,10]]},"DOI":"10.1109\/vlsisoc.2011.6081651","type":"proceedings-article","created":{"date-parts":[[2011,11,21]],"date-time":"2011-11-21T21:42:27Z","timestamp":1321911747000},"page":"78-81","source":"Crossref","is-referenced-by-count":3,"title":["Topology synthesis of analog circuits with yield optimization and evaluation using pareto fronts"],"prefix":"10.1109","author":[{"given":"Oliver","family":"Mitea","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Markus","family":"Meissner","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lars","family":"Hedrich","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","article-title":"The sizing rules method for analog integrated circuit design","author":"graeg","year":"0","journal-title":"ICCAD '01"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2006.1692876"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/43.372370"},{"article-title":"Analog design centering and sizing","year":"2007","author":"graeb","key":"ref13"},{"year":"0","key":"ref14"},{"key":"ref4","article-title":"Topology synthesis of analog circuits based on adaptively generated building blocks","author":"das","year":"2010","journal-title":"DAC ACM"},{"key":"ref3","article-title":"Simultaneous multi-topology multi-objective sizing across thousands of analog circuit topologies","author":"mc conaghy","year":"2007","journal-title":"DAC"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2011.5763264"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/1118299.1118463"},{"key":"ref8","article-title":"Symbolic Analysis of Nonlinear Analog Circuits by Simplification of Nested Expressions","author":"popp","year":"0","journal-title":"SMACD'00"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-3962-9"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2001.921944"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ASIC.1989.123242"},{"year":"0","key":"ref9"}],"event":{"name":"2011 IEEE\/IFIP 19th International Conference on VLSI and System-on-Chip (VLSI-SoC)","start":{"date-parts":[[2011,10,3]]},"location":"Kowloon, Hong Kong","end":{"date-parts":[[2011,10,5]]}},"container-title":["2011 IEEE\/IFIP 19th International Conference on VLSI and System-on-Chip"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6069623\/6081592\/06081651.pdf?arnumber=6081651","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T17:20:50Z","timestamp":1490116850000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6081651\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,10]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/vlsisoc.2011.6081651","relation":{},"subject":[],"published":{"date-parts":[[2011,10]]}}}