{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T13:53:38Z","timestamp":1725544418334},"reference-count":13,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,10]]},"DOI":"10.1109\/vlsisoc.2011.6081674","type":"proceedings-article","created":{"date-parts":[[2011,11,21]],"date-time":"2011-11-21T21:42:27Z","timestamp":1321911747000},"page":"192-195","source":"Crossref","is-referenced-by-count":0,"title":["A fault-tolerant network-on-chip design using dynamic reconfiguration of partial-faulty routing resources"],"prefix":"10.1109","author":[{"family":"Zhiliang Qian","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Ying Fei Teh","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Chi-Ying Tsui","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cdt.2008.0082"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2007.30"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2005.22"},{"year":"0","key":"ref13"},{"key":"ref4","first-page":"441","article-title":"A reconfigurable routing algorithm for a fault-tolerant 2d-mesh network-on-chip","author":"zhen","year":"2008","journal-title":"Proc DAC"},{"key":"ref3","doi-asserted-by":"crossref","first-page":"812","DOI":"10.1145\/1629911.1630119","article-title":"vicis: a reliable network for unreliable silicon","author":"fick","year":"2009","journal-title":"2009 46th ACM\/IEEE Design Automation Conference dac"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2009.5090627"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2008.4542002"},{"key":"ref8","first-page":"72","article-title":"Fault-tolerant router with built-in self-test\/self-diagnosis and fault-isolation circuits for 2d-mesh based chip multiprocessor systems","author":"lin","year":"2009","journal-title":"Proc VLSI-DAT"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2048399"},{"key":"ref2","first-page":"93","article-title":"Exploring fault-tolerant network-on-chip architectures","author":"park","year":"2006","journal-title":"Proc DSN"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2002.998307"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/HSC.1998.666245"}],"event":{"name":"2011 IEEE\/IFIP 19th International Conference on VLSI and System-on-Chip (VLSI-SoC)","start":{"date-parts":[[2011,10,3]]},"location":"Kowloon, Hong Kong","end":{"date-parts":[[2011,10,5]]}},"container-title":["2011 IEEE\/IFIP 19th International Conference on VLSI and System-on-Chip"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6069623\/6081592\/06081674.pdf?arnumber=6081674","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,20]],"date-time":"2017-06-20T10:06:56Z","timestamp":1497953216000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6081674\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,10]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/vlsisoc.2011.6081674","relation":{},"subject":[],"published":{"date-parts":[[2011,10]]}}}