{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,28]],"date-time":"2026-03-28T16:49:37Z","timestamp":1774716577761,"version":"3.50.1"},"reference-count":9,"publisher":"IEEE","license":[{"start":{"date-parts":[[2022,6,12]],"date-time":"2022-06-12T00:00:00Z","timestamp":1654992000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,6,12]],"date-time":"2022-06-12T00:00:00Z","timestamp":1654992000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2022,6,12]]},"DOI":"10.1109\/vlsitechnologyandcir46769.2022.9830277","type":"proceedings-article","created":{"date-parts":[[2022,7,22]],"date-time":"2022-07-22T16:42:52Z","timestamp":1658508172000},"page":"16-17","source":"Crossref","is-referenced-by-count":44,"title":["A 17\u201395.6 TOPS\/W Deep Learning Inference Accelerator with Per-Vector Scaled 4-bit Quantization for Transformers in 5nm"],"prefix":"10.1109","author":[{"given":"Ben","family":"Keller","sequence":"first","affiliation":[{"name":"NVIDIA,Santa Clara,CA,USA"}]},{"given":"Rangharajan","family":"Venkatesan","sequence":"additional","affiliation":[{"name":"NVIDIA,Santa Clara,CA,USA"}]},{"given":"Steve","family":"Dai","sequence":"additional","affiliation":[{"name":"NVIDIA,Santa Clara,CA,USA"}]},{"given":"Stephen G.","family":"Tell","sequence":"additional","affiliation":[{"name":"NVIDIA,Durham,NC,USA"}]},{"given":"Brian","family":"Zimmer","sequence":"additional","affiliation":[{"name":"NVIDIA,Santa Clara,CA,USA"}]},{"given":"William J.","family":"Dally","sequence":"additional","affiliation":[{"name":"NVIDIA,Santa Clara,CA,USA"}]},{"given":"C.","family":"Thomas Gray","sequence":"additional","affiliation":[{"name":"NVIDIA,Durham,NC,USA"}]},{"given":"Brucek","family":"Khailany","sequence":"additional","affiliation":[{"name":"NVIDIA,Austin,TX,USA"}]}],"member":"263","reference":[{"key":"ref4","author":"dai","year":"2021","journal-title":"MLSys"},{"key":"ref3","author":"agrawal","year":"2021","journal-title":"ISSCC"},{"key":"ref6","author":"venkatesan","year":"2019","journal-title":"ICCAD"},{"key":"ref5","author":"stevens","year":"2021","journal-title":"DAC"},{"key":"ref8","author":"park","year":"2021","journal-title":"ISSCC"},{"key":"ref7","author":"mo","year":"2021","journal-title":"ISSCC"},{"key":"ref2","author":"dosovitskiy","year":"2021","journal-title":"ICLRE"},{"key":"ref9","author":"lin","year":"2020","journal-title":"ISSCC"},{"key":"ref1","author":"vaswani","year":"2017","journal-title":"NeurIPS"}],"event":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","location":"Honolulu, HI, USA","start":{"date-parts":[[2022,6,12]]},"end":{"date-parts":[[2022,6,17]]}},"container-title":["2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9830116\/9830138\/09830277.pdf?arnumber=9830277","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,11,3]],"date-time":"2022-11-03T22:59:32Z","timestamp":1667516372000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9830277\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,6,12]]},"references-count":9,"URL":"https:\/\/doi.org\/10.1109\/vlsitechnologyandcir46769.2022.9830277","relation":{},"subject":[],"published":{"date-parts":[[2022,6,12]]}}}