{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,7]],"date-time":"2024-09-07T19:13:30Z","timestamp":1725736410391},"reference-count":6,"publisher":"IEEE","license":[{"start":{"date-parts":[[2022,6,12]],"date-time":"2022-06-12T00:00:00Z","timestamp":1654992000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,6,12]],"date-time":"2022-06-12T00:00:00Z","timestamp":1654992000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2022,6,12]]},"DOI":"10.1109\/vlsitechnologyandcir46769.2022.9830470","type":"proceedings-article","created":{"date-parts":[[2022,7,22]],"date-time":"2022-07-22T16:42:52Z","timestamp":1658508172000},"page":"138-139","source":"Crossref","is-referenced-by-count":2,"title":["A 7Gbps SCA-Resistant Multiplicative-Masked AES Engine in Intel 4 CMOS"],"prefix":"10.1109","author":[{"given":"Raghavan","family":"Kumar","sequence":"first","affiliation":[{"name":"Intel Corporation,Circuits Research Lab,Hillsboro,OR,USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Vikram","family":"Suresh","sequence":"additional","affiliation":[{"name":"Intel Corporation,Circuits Research Lab,Hillsboro,OR,USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sachin","family":"Taneja","sequence":"additional","affiliation":[{"name":"Intel Corporation,Circuits Research Lab,Hillsboro,OR,USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mark","family":"Anders","sequence":"additional","affiliation":[{"name":"Intel Corporation,Circuits Research Lab,Hillsboro,OR,USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Steven","family":"Hsu","sequence":"additional","affiliation":[{"name":"Intel Corporation,Circuits Research Lab,Hillsboro,OR,USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Amit","family":"Agarwal","sequence":"additional","affiliation":[{"name":"Intel Corporation,Circuits Research Lab,Hillsboro,OR,USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Vivek","family":"De","sequence":"additional","affiliation":[{"name":"Intel Corporation,Circuits Research Lab,Hillsboro,OR,USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sanu","family":"Mathew","sequence":"additional","affiliation":[{"name":"Intel Corporation,Circuits Research Lab,Hillsboro,OR,USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"journal-title":"JSSC","year":"2020","author":"kumar","key":"ref4"},{"journal-title":"CHES","year":"2002","author":"golic","key":"ref3"},{"journal-title":"ISSCC","year":"2022","author":"kumar","key":"ref6"},{"journal-title":"ISSCC","year":"2011","author":"doulcier-verdier","key":"ref5"},{"journal-title":"CHES","year":"2001","author":"akkar","key":"ref2"},{"journal-title":"ACNS","year":"2008","author":"canright","key":"ref1"}],"event":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","start":{"date-parts":[[2022,6,12]]},"location":"Honolulu, HI, USA","end":{"date-parts":[[2022,6,17]]}},"container-title":["2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9830116\/9830138\/09830470.pdf?arnumber=9830470","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,10,3]],"date-time":"2022-10-03T20:39:44Z","timestamp":1664829584000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9830470\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,6,12]]},"references-count":6,"URL":"https:\/\/doi.org\/10.1109\/vlsitechnologyandcir46769.2022.9830470","relation":{},"subject":[],"published":{"date-parts":[[2022,6,12]]}}}