{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,9]],"date-time":"2026-04-09T14:46:27Z","timestamp":1775745987742,"version":"3.50.1"},"reference-count":3,"publisher":"IEEE","license":[{"start":{"date-parts":[[2024,6,16]],"date-time":"2024-06-16T00:00:00Z","timestamp":1718496000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,6,16]],"date-time":"2024-06-16T00:00:00Z","timestamp":1718496000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2024,6,16]]},"DOI":"10.1109\/vlsitechnologyandcir46783.2024.10631515","type":"proceedings-article","created":{"date-parts":[[2024,8,26]],"date-time":"2024-08-26T17:23:31Z","timestamp":1724693011000},"page":"1-2","source":"Crossref","is-referenced-by-count":12,"title":["MINOTAUR: An Edge Transformer Inference and Training Accelerator with 12 MBytes On-Chip Resistive RAM and Fine-Grained Spatiotemporal Power Gating"],"prefix":"10.1109","author":[{"given":"Kartik","family":"Prabhu","sequence":"first","affiliation":[{"name":"Stanford University,CA,USA"}]},{"given":"Robert M.","family":"Radway","sequence":"additional","affiliation":[{"name":"Stanford University,CA,USA"}]},{"given":"Jeffrey","family":"Yu","sequence":"additional","affiliation":[{"name":"Stanford University,CA,USA"}]},{"given":"Kai","family":"Bartolone","sequence":"additional","affiliation":[{"name":"Stanford University,CA,USA"}]},{"given":"Massimo","family":"Giordano","sequence":"additional","affiliation":[{"name":"Stanford University,CA,USA"}]},{"given":"Fabian","family":"Peddinghaus","sequence":"additional","affiliation":[{"name":"Stanford University,CA,USA"}]},{"given":"Yonatan","family":"Urman","sequence":"additional","affiliation":[{"name":"Stanford University,CA,USA"}]},{"given":"Win-San","family":"Khwa","sequence":"additional","affiliation":[{"name":"TSMC,Hsinchu,Taiwan"}]},{"given":"Yu-Der","family":"Chih","sequence":"additional","affiliation":[{"name":"TSMC,Hsinchu,Taiwan"}]},{"given":"Meng-Fan","family":"Chang","sequence":"additional","affiliation":[{"name":"TSMC,Hsinchu,Taiwan"}]},{"given":"Subhasish","family":"Mitra","sequence":"additional","affiliation":[{"name":"Stanford University,CA,USA"}]},{"given":"Priyanka","family":"Raina","sequence":"additional","affiliation":[{"name":"Stanford University,CA,USA"}]}],"member":"263","reference":[{"key":"ref1","author":"Gustafson","year":"2017","journal-title":"Supercomp. Front. Innov."},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.5860\/choice.45-0602"},{"key":"ref3","author":"Prabhu","year":"2022","journal-title":"JSSC"}],"event":{"name":"2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","location":"Honolulu, HI, USA","start":{"date-parts":[[2024,6,16]]},"end":{"date-parts":[[2024,6,20]]}},"container-title":["2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/10631290\/10631310\/10631515.pdf?arnumber=10631515","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,5]],"date-time":"2025-06-05T04:22:05Z","timestamp":1749097325000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10631515\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,6,16]]},"references-count":3,"URL":"https:\/\/doi.org\/10.1109\/vlsitechnologyandcir46783.2024.10631515","relation":{},"subject":[],"published":{"date-parts":[[2024,6,16]]}}}