{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T09:47:31Z","timestamp":1725443251101},"reference-count":12,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/vtest.2004.1299232","type":"proceedings-article","created":{"date-parts":[[2004,6,10]],"date-time":"2004-06-10T14:19:45Z","timestamp":1086877185000},"page":"103-108","source":"Crossref","is-referenced-by-count":12,"title":["Yield analysis of logic circuits"],"prefix":"10.1109","author":[{"given":"D.","family":"Appello","sequence":"first","affiliation":[]},{"given":"A.","family":"Fudoli","sequence":"additional","affiliation":[]},{"given":"K.","family":"Giarda","sequence":"additional","affiliation":[]},{"given":"E.","family":"Gizdarski","sequence":"additional","affiliation":[]},{"given":"B.","family":"Mathew","sequence":"additional","affiliation":[]},{"given":"V.","family":"Tancorre","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"journal-title":"Digital System Testing and Testable Design","year":"1990","author":"abramovici","key":"3"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1999.805768"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/54.606006"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2002.1041768"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/43.229763"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.2000.843860"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/54.32421"},{"journal-title":"Teradyne-Standard Test Data Format Specification","year":"1995","key":"4"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/66.641490"},{"key":"8","first-page":"65","article-title":"A practical evaluation of IDDQ test strategies for deep submicron production test application. Experiences and targets from the field","author":"appello","year":"2003","journal-title":"IEEE European Test Workshop"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1994.527983"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1995.529877"}],"event":{"name":"22nd IEEE VLSI Test Symposium, 2004.","location":"Napa Valley, CA, USA"},"container-title":["22nd IEEE VLSI Test Symposium, 2004. Proceedings."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/9095\/28867\/01299232.pdf?arnumber=1299232","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,13]],"date-time":"2017-03-13T21:08:47Z","timestamp":1489439327000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1299232\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/vtest.2004.1299232","relation":{},"subject":[]}}