{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T12:06:36Z","timestamp":1759147596385,"version":"3.28.0"},"reference-count":16,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/vtest.2004.1299235","type":"proceedings-article","created":{"date-parts":[[2004,6,10]],"date-time":"2004-06-10T10:19:45Z","timestamp":1086862785000},"page":"123-128","source":"Crossref","is-referenced-by-count":22,"title":["New test methodology for resistive open defect detection in memory address decoders"],"prefix":"10.1109","author":[{"given":"M.","family":"Azimane","sequence":"first","affiliation":[]},{"given":"A.K.","family":"Majhi","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2002.1033788"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1049\/ip-cds:19971147"},{"journal-title":"Testing of Random Access Memories","year":"1999","author":"azimane","key":"13"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.2000.843856"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2000.894303"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2001.966731"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/54.587738"},{"journal-title":"High Performance Memory Testing","year":"2002","author":"adams","key":"2"},{"journal-title":"Testing Semiconductor Memories Theory and Practice","year":"1998","author":"van de goor","key":"1"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1998.743133"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2001.990255"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2001.915069"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2001.966638"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1998.743137"},{"key":"9","first-page":"23","article-title":"Defect-oriented dynamic fault models for embedded-SRAMs","author":"boni","year":"2003","journal-title":"Proc Of European Test Workshop"},{"key":"8","doi-asserted-by":"crossref","first-page":"381","DOI":"10.1023\/A:1008322103755","article-title":"Detection of delay faults in memory address decoders","volume":"16","author":"gizdarski","year":"2000","journal-title":"Journal of Electronic Testing Theory and Applications"}],"event":{"name":"22nd IEEE VLSI Test Symposium, 2004.","location":"Napa Valley, CA, USA"},"container-title":["22nd IEEE VLSI Test Symposium, 2004. Proceedings."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/9095\/28867\/01299235.pdf?arnumber=1299235","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,16]],"date-time":"2017-06-16T03:57:24Z","timestamp":1497585444000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1299235\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1109\/vtest.2004.1299235","relation":{},"subject":[]}}