{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T16:03:53Z","timestamp":1730304233694,"version":"3.28.0"},"reference-count":22,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/vtest.2004.1299264","type":"proceedings-article","created":{"date-parts":[[2004,6,10]],"date-time":"2004-06-10T14:19:45Z","timestamp":1086877185000},"page":"353-358","source":"Crossref","is-referenced-by-count":7,"title":["Hybrid BIST for system-on-a-chip using an embedded FPGA core"],"prefix":"10.1109","author":[{"family":"Gang Zeng","sequence":"first","affiliation":[]},{"given":"H.","family":"Ito","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"year":"2003","key":"ref10","article-title":"Triscend Embedded Programmable Logic Core for SoC Applications"},{"journal-title":"A Designer's Guide to Built-In Self-Test","year":"2002","author":"stroud","key":"ref11"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2002.1181712"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1996.556962"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2002.1041826"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.2003.1197675"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2002.1041756"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/43.918212"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1996.569803"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1998.743304"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2001.929724"},{"key":"ref3","first-page":"187","article-title":"A Hybrid ASIC and FPGA Architecture","author":"zuchowski","year":"2002","journal-title":"Proc of IEEE\/ACM International Conference on Computer Aided Design (ICCAD)"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.2000.843824"},{"key":"ref5","first-page":"65","article-title":"DATE 2001 Roundtable: Adding Reconfigurable Logic to SOC Design","volume":"18","year":"2001","journal-title":"IEEE Design&Test of Computers"},{"year":"0","key":"ref8"},{"key":"ref7","first-page":"36","article-title":"Energy Advantages of Microprocessor Platforms with On-Chip Configurable Logic","volume":"19","author":"greg","year":"2002","journal-title":"IEEE Design&test"},{"key":"ref2","article-title":"Using Embedded FPGAs for SOC Yield Improvement","author":"abramovici","year":"2002","journal-title":"Proc ACM\/IEEE Design Automation Conf (DAC)"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1998.743146"},{"year":"2002","key":"ref9","article-title":"IBM Licenses Embedded FPGA Cores from Xilinx for Use in SoC ASICs"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2000.894197"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/DFTVS.2003.1250149"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1999.805650"}],"event":{"name":"22nd IEEE VLSI Test Symposium, 2004.","location":"Napa Valley, CA, USA"},"container-title":["22nd IEEE VLSI Test Symposium, 2004. Proceedings."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/9095\/28867\/01299264.pdf?arnumber=1299264","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,14]],"date-time":"2017-03-14T01:29:51Z","timestamp":1489454991000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1299264\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":22,"URL":"https:\/\/doi.org\/10.1109\/vtest.2004.1299264","relation":{},"subject":[]}}