{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,19]],"date-time":"2025-03-19T15:37:53Z","timestamp":1742398673536,"version":"3.28.0"},"reference-count":8,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/vts.2002.1011114","type":"proceedings-article","created":{"date-parts":[[2003,6,25]],"date-time":"2003-06-25T20:42:54Z","timestamp":1056573774000},"page":"75-80","source":"Crossref","is-referenced-by-count":17,"title":["Yield-reliability modeling: experimental verification and application to burn-in reduction"],"prefix":"10.1109","author":[{"given":"T.S.","family":"Barnett","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"A.D.","family":"Singh","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M.","family":"Grady","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"K.","family":"Purdy","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","first-page":"1","article-title":"Microprocessor Reliability Performance as a Function of Die Location for a 0.25?, Five Layer Metal CMOS Logic Process","author":"riordan","year":"1999","journal-title":"Proceedings International Reliability Physics Symposium"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2001.923457"},{"key":"ref6","doi-asserted-by":"crossref","first-page":"1817","DOI":"10.1109\/5.705525","article-title":"Defect Tolerant VLSI Circuits: Techniques and Yield Analysis","volume":"86","author":"koren","year":"1998","journal-title":"Proceedings of the IEEE"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/PROC.1983.12619"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2001.966650"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-6799-8_1"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/43.277614"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/RELPHY.1992.187656"}],"event":{"name":"20th IEEE VLSI Test Symposium (VTS 2002)","acronym":"VTEST-02","location":"Monterey, CA, USA"},"container-title":["Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/7901\/21789\/01011114.pdf?arnumber=1011114","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,15]],"date-time":"2017-06-15T22:40:43Z","timestamp":1497566443000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1011114\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":8,"URL":"https:\/\/doi.org\/10.1109\/vts.2002.1011114","relation":{},"subject":[]}}