{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T20:45:14Z","timestamp":1729629914661,"version":"3.28.0"},"reference-count":16,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/vts.2002.1011144","type":"proceedings-article","created":{"date-parts":[[2003,6,25]],"date-time":"2003-06-25T16:42:54Z","timestamp":1056559374000},"page":"237-243","source":"Crossref","is-referenced-by-count":15,"title":["Program slicing for hierarchical test generation"],"prefix":"10.1109","author":[{"given":"V.M.","family":"Vedula","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J.A.","family":"Abraham","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J.","family":"Bhadra","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/WPC.2001.921713"},{"key":"ref11","first-page":"479","article-title":"A Program Decomposition Scheme with Applications to Software Modification and Testing","volume":"2","author":"lyle","year":"1989","journal-title":"Proc of the Hawaii Intl Conf on System Sciences"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/32.83912"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/32.588543"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/54.199804"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1993.470660"},{"key":"ref16","first-page":"185","article-title":"A Graphical Parallel Composition Operator for Process Algebras","author":"garavel","year":"1999","journal-title":"Proc FORTE\/PSTV`98"},{"key":"ref4","first-page":"2585","article-title":"Program Slicing on VHDL Descriptions and Its Evaluation","volume":"e81 a","author":"ichinose","year":"1998","journal-title":"IEICE Trans Fund"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/113445.113455"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2002.998380"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-48153-2_22"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1992.227793"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/12.54847"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TSE.1984.5010248"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1997.639687"},{"key":"ref9","doi-asserted-by":"crossref","first-page":"1144","DOI":"10.1109\/43.536720","article-title":"Hierarchical Test Generation under Architectural Level Functional Constraints","volume":"15","author":"lee","year":"1996","journal-title":"IEEE Trans on Computer-Aided Design of Integrated Circuits and Systems"}],"event":{"name":"20th IEEE VLSI Test Symposium (VTS 2002)","acronym":"VTEST-02","location":"Monterey, CA, USA"},"container-title":["Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/7901\/21789\/01011144.pdf?arnumber=1011144","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,15]],"date-time":"2017-06-15T18:40:44Z","timestamp":1497552044000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1011144\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1109\/vts.2002.1011144","relation":{},"subject":[]}}