{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,4]],"date-time":"2025-11-04T10:22:27Z","timestamp":1762251747435},"reference-count":13,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,5]]},"DOI":"10.1109\/vts.2011.5783724","type":"proceedings-article","created":{"date-parts":[[2011,6,7]],"date-time":"2011-06-07T16:35:25Z","timestamp":1307464525000},"page":"219-224","source":"Crossref","is-referenced-by-count":24,"title":["Design and implementation of a time-division multiplexing scan architecture using serializer and deserializer in GPU chips"],"prefix":"10.1109","author":[{"given":"Amit","family":"Sanghani","sequence":"first","affiliation":[]},{"given":"Bo","family":"Yang","sequence":"additional","affiliation":[]},{"given":"Karthikeyan","family":"Natarajan","sequence":"additional","affiliation":[]},{"given":"Chunsheng","family":"Liu","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2004.60"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2004.1387356"},{"key":"ref12","first-page":"46","article-title":"Thermal-Aware Testing of Network-on-Chip Using Multiple Clocking","author":"liu","year":"2006","journal-title":"Proc VLSI Test Symp"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1093\/ietisy\/e91-d.7.2008"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1017\/CBO9780511816321"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2002.1011104"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2003.818122"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.2003.1197640"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1023\/A:1022829321216"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2003.1270904"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2002.1041775"},{"key":"ref1","first-page":"1.4.1","article-title":"Test resource partitioning for scan architectures using bandwidth matching","author":"khoche","year":"2002","journal-title":"Dig Int Workshop Test Resource Partitioning"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.834228"}],"event":{"name":"2011 IEEE VLSI Test Symposium (VTS)","start":{"date-parts":[[2011,5,1]]},"location":"Dana Point, CA, USA","end":{"date-parts":[[2011,5,5]]}},"container-title":["29th VLSI Test Symposium"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5772241\/5783722\/05783724.pdf?arnumber=5783724","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T02:52:57Z","timestamp":1490064777000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5783724\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,5]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/vts.2011.5783724","relation":{},"subject":[],"published":{"date-parts":[[2011,5]]}}}