{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,14]],"date-time":"2025-06-14T22:25:16Z","timestamp":1749939916907,"version":"3.28.0"},"reference-count":14,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,5]]},"DOI":"10.1109\/vts.2011.5783761","type":"proceedings-article","created":{"date-parts":[[2011,6,7]],"date-time":"2011-06-07T16:35:25Z","timestamp":1307464525000},"page":"90-95","source":"Crossref","is-referenced-by-count":6,"title":["Efficient and product-representative timing model validation"],"prefix":"10.1109","author":[{"family":"Eun Jung Jang","sequence":"first","affiliation":[]},{"given":"Anne","family":"Gattiker","sequence":"additional","affiliation":[]},{"given":"Sani","family":"Nassif","sequence":"additional","affiliation":[]},{"given":"Jacob A.","family":"Abraham","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"doi-asserted-by":"publisher","key":"ref10","DOI":"10.1023\/A:1012259227622"},{"key":"ref11","doi-asserted-by":"crossref","first-page":"384","DOI":"10.1145\/1278480.1278580","article-title":"design-silicon timing correlation a data mining perspective","author":"wang","year":"2007","journal-title":"2007 44th ACM\/IEEE Design Automation Conference DAC"},{"key":"ref12","first-page":"291","article-title":"Weighted random robust path delay testing of synthesized multilevelcircuits","author":"wang","year":"1994","journal-title":"Proceedings of the IEEE VLSI Test Symposium 1994"},{"doi-asserted-by":"publisher","key":"ref13","DOI":"10.1109\/ICCAD.2008.4681644"},{"doi-asserted-by":"publisher","key":"ref14","DOI":"10.1023\/A:1008365428314"},{"doi-asserted-by":"publisher","key":"ref4","DOI":"10.1109\/TSM.2005.863244"},{"doi-asserted-by":"publisher","key":"ref3","DOI":"10.1145\/1391469.1391566"},{"key":"ref6","first-page":"698","article-title":"A neutral netlist of 10 combinational benchmark circuits and a target translator in Fortran","volume":"663","author":"brglez","year":"1985","journal-title":"Proc of International Symposium on Circuits and Systems"},{"doi-asserted-by":"publisher","key":"ref5","DOI":"10.1145\/589434.589435"},{"doi-asserted-by":"publisher","key":"ref8","DOI":"10.1109\/43.402498"},{"key":"ref7","first-page":"33","article-title":"High speed test structures for in-line process monitoring and model calibration","author":"ketchen","year":"2005","journal-title":"IEEE Proc ICMTS"},{"doi-asserted-by":"publisher","key":"ref2","DOI":"10.1109\/TEST.1998.743141"},{"key":"ref1","first-page":"399","article-title":"Characterizing process variation in nanome-ter CMOS","author":"agarwal","year":"2007","journal-title":"Proceedings of the 44th Annual Design Automation Conference"},{"doi-asserted-by":"publisher","key":"ref9","DOI":"10.1109\/ASICON.2009.5351332"}],"event":{"name":"2011 IEEE VLSI Test Symposium (VTS)","start":{"date-parts":[[2011,5,1]]},"location":"Dana Point, CA, USA","end":{"date-parts":[[2011,5,5]]}},"container-title":["29th VLSI Test Symposium"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5772241\/5783722\/05783761.pdf?arnumber=5783761","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,19]],"date-time":"2017-06-19T21:16:01Z","timestamp":1497906961000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5783761\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,5]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/vts.2011.5783761","relation":{},"subject":[],"published":{"date-parts":[[2011,5]]}}}