{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,4,22]],"date-time":"2025-04-22T19:25:34Z","timestamp":1745349934840},"reference-count":5,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013,4]]},"DOI":"10.1109\/vts.2013.6548879","type":"proceedings-article","created":{"date-parts":[[2013,7,9]],"date-time":"2013-07-09T10:59:10Z","timestamp":1373367550000},"page":"1-6","source":"Crossref","is-referenced-by-count":2,"title":["Experiments and analysis to characterize logic state retention limitations in 28nm process node"],"prefix":"10.1109","author":[{"given":"S.","family":"Dasnurkar","sequence":"first","affiliation":[]},{"given":"A.","family":"Datta","sequence":"additional","affiliation":[]},{"given":"M.","family":"Abu-Rahma","sequence":"additional","affiliation":[]},{"given":"H.","family":"Nguyen","sequence":"additional","affiliation":[]},{"given":"M.","family":"Villafana","sequence":"additional","affiliation":[]},{"given":"H.","family":"Rasouli","sequence":"additional","affiliation":[]},{"given":"S.","family":"Tamjidi","sequence":"additional","affiliation":[]},{"family":"Ming Cai","sequence":"additional","affiliation":[]},{"given":"S.","family":"Sengupta","sequence":"additional","affiliation":[]},{"given":"P. R.","family":"Chidambaram","sequence":"additional","affiliation":[]},{"given":"R.","family":"Thirumala","sequence":"additional","affiliation":[]},{"given":"N.","family":"Kulkarni","sequence":"additional","affiliation":[]},{"given":"P.","family":"Seeram","sequence":"additional","affiliation":[]},{"given":"P.","family":"Bhadri","sequence":"additional","affiliation":[]},{"given":"P.","family":"Patel","sequence":"additional","affiliation":[]},{"family":"Sei Seung Yoon","sequence":"additional","affiliation":[]},{"given":"E.","family":"Terzioglu","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/4.982424"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2010.5434076"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2010.5703432"},{"journal-title":"Fundamentals of Modern VLSI Devices","year":"1998","author":"taur","key":"5"},{"key":"4","article-title":"A 280mv-to-1. 2v wide-operating-range ia-32 processor in 32nm cmos","author":"jain","year":"2012","journal-title":"ISSC"}],"event":{"name":"2013 IEEE 31st VLSI Test Symposium (VTS)","start":{"date-parts":[[2013,4,29]]},"location":"Berkeley, CA","end":{"date-parts":[[2013,5,2]]}},"container-title":["2013 IEEE 31st VLSI Test Symposium (VTS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6530960\/6548868\/06548879.pdf?arnumber=6548879","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,22]],"date-time":"2017-03-22T21:22:38Z","timestamp":1490217758000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6548879\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,4]]},"references-count":5,"URL":"https:\/\/doi.org\/10.1109\/vts.2013.6548879","relation":{},"subject":[],"published":{"date-parts":[[2013,4]]}}}