{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T09:09:49Z","timestamp":1725527389076},"reference-count":12,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013,4]]},"DOI":"10.1109\/vts.2013.6548880","type":"proceedings-article","created":{"date-parts":[[2013,7,9]],"date-time":"2013-07-09T10:59:10Z","timestamp":1373367550000},"page":"1-6","source":"Crossref","is-referenced-by-count":0,"title":["Testing retention flip-flops in power-gated designs"],"prefix":"10.1109","author":[{"family":"Hao-Wen Hsu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Shih-Hua Kuo","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Wen-Hsiang Chang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Shi-Hao Chen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Ming-Tung Chang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mango C.-T","family":"Chao","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2010.5654118"},{"key":"2","first-page":"141","article-title":"Subthreshold leakage modeling and reduction techniques","author":"kao","year":"2002","journal-title":"IEEE\/ACM International Conference on Computer Aided Design"},{"journal-title":"Synopsys HSPICE Version C-2009 03-SP1","year":"0","key":"10"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2002.808156"},{"key":"7","article-title":"Power-aware testing and test strategies for low power devices","author":"girard","year":"2009","journal-title":"Springer"},{"key":"6","first-page":"435","article-title":"Testing of level shifters in multiple voltage designs","author":"zain ali","year":"2007","journal-title":"IEEE International Conference on Electronics Circuits and Systems"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/ETS.2011.63"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cdt:20060147"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1145\/775832.775947"},{"key":"8","first-page":"684","article-title":"Fault modeling and testing of retention flip-flops in low power designs","author":"bai","year":"2009","journal-title":"Asia and South Pacific Design Automation Conference"},{"journal-title":"Cadence Encounter Version 8 1","year":"0","key":"11"},{"journal-title":"Synopsys Hercules Version B-2008 09 SP3 HF3 24036","year":"0","key":"12"}],"event":{"name":"2013 IEEE 31st VLSI Test Symposium (VTS)","start":{"date-parts":[[2013,4,29]]},"location":"Berkeley, CA","end":{"date-parts":[[2013,5,2]]}},"container-title":["2013 IEEE 31st VLSI Test Symposium (VTS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6530960\/6548868\/06548880.pdf?arnumber=6548880","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,22]],"date-time":"2017-03-22T21:22:41Z","timestamp":1490217761000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6548880\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,4]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/vts.2013.6548880","relation":{},"subject":[],"published":{"date-parts":[[2013,4]]}}}