{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T21:54:59Z","timestamp":1729634099177,"version":"3.28.0"},"reference-count":16,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013,4]]},"DOI":"10.1109\/vts.2013.6548883","type":"proceedings-article","created":{"date-parts":[[2013,7,9]],"date-time":"2013-07-09T14:59:10Z","timestamp":1373381950000},"page":"1-6","source":"Crossref","is-referenced-by-count":0,"title":["Improving test generation by use of majority gates"],"prefix":"10.1109","author":[{"given":"P.","family":"Wohl","sequence":"first","affiliation":[]},{"given":"J. A.","family":"Waicukauski","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2010.5699236"},{"year":"0","key":"16"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/FTCS.1988.5293"},{"key":"14","article-title":"Test quality for high-level structural test","author":"al-yamani","year":"2004","journal-title":"High-Level Design Validation and Test Workshop"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/DDECS.2007.4295316"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/43.108617"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.882600"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1145\/1837274.1837366"},{"journal-title":"Semiconductor Industry Association (2007) International Technology Roadmap for Semiconductors (ITRS","year":"0","key":"1"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2007.891081"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1973.223705"},{"key":"6","doi-asserted-by":"crossref","first-page":"1357","DOI":"10.1049\/el:19960929","article-title":"binary sorter by majority gate","volume":"32","author":"kit","year":"1996","journal-title":"Electronics Letters"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2007.915203"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2010.5699226"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/IMS3TW.2008.4581630"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/PGEC.1964.263829"}],"event":{"name":"2013 IEEE 31st VLSI Test Symposium (VTS)","start":{"date-parts":[[2013,4,29]]},"location":"Berkeley, CA","end":{"date-parts":[[2013,5,2]]}},"container-title":["2013 IEEE 31st VLSI Test Symposium (VTS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6530960\/6548868\/06548883.pdf?arnumber=6548883","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,21]],"date-time":"2017-06-21T15:58:10Z","timestamp":1498060690000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6548883\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,4]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1109\/vts.2013.6548883","relation":{},"subject":[],"published":{"date-parts":[[2013,4]]}}}