{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T00:01:20Z","timestamp":1729641680582,"version":"3.28.0"},"reference-count":24,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013,4]]},"DOI":"10.1109\/vts.2013.6548927","type":"proceedings-article","created":{"date-parts":[[2013,7,9]],"date-time":"2013-07-09T10:59:10Z","timestamp":1373367550000},"page":"1-6","source":"Crossref","is-referenced-by-count":0,"title":["A hybrid ECC and redundancy technique for reducing refresh power of DRAMs"],"prefix":"10.1109","author":[{"family":"Yun-Chao Yu","sequence":"first","affiliation":[]},{"family":"Chih-Sheng Hou","sequence":"additional","affiliation":[]},{"family":"Li-Jung Chang","sequence":"additional","affiliation":[]},{"family":"Jin-Fu Li","sequence":"additional","affiliation":[]},{"family":"Chih-Yen Lo","sequence":"additional","affiliation":[]},{"family":"Ding-Ming Kwai","sequence":"additional","affiliation":[]},{"family":"Yung-Fa Chou","sequence":"additional","affiliation":[]},{"family":"Cheng-Wen Wu","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2009.5118313"},{"key":"22","doi-asserted-by":"crossref","first-page":"329","DOI":"10.1109\/JSSC.2002.807170","article-title":"A low-power 256-Mb SDRAM with an on-chip thermometer and biased refrence line sensing scheme","volume":"38","author":"kim","year":"2003","journal-title":"IEEE Jour of Solid-State Circuits"},{"key":"17","doi-asserted-by":"crossref","first-page":"1006","DOI":"10.1109\/TVLSI.2003.817524","article-title":"Block-based multiperiod dynamic memory design for low data-retention power","volume":"11","author":"kim","year":"2003","journal-title":"IEEE Trans on VLSI Systems"},{"key":"23","doi-asserted-by":"publisher","DOI":"10.1016\/S0019-9958(60)90287-4"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1109\/DFTVS.1999.802898"},{"journal-title":"International Technology Roadmap for Semiconductors (ITRS)","year":"2010","key":"24"},{"key":"15","article-title":"Generalization of an enhanced ECC methodology for low power PSRAM","author":"chen","year":"2012","journal-title":"IEEE Trans on Computers"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/ASSCC.2006.357915"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/IOLTS.2012.6313845"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2006.1696093"},{"key":"11","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/2366231.2337161","article-title":"RAIDR: Retention-aware intelligent DRAM refresh","author":"liu","year":"2012","journal-title":"Proc of Int'l Symp on Computer Architecture"},{"key":"12","doi-asserted-by":"crossref","first-page":"83","DOI":"10.1145\/1816038.1815973","article-title":"Reducing cache power with low-cost, multi-bit errorcorrecting codes","author":"wilkerson","year":"2010","journal-title":"Proc of Int'l Symp on Computer Architecture"},{"journal-title":"DDR3 SDRAM","year":"0","key":"21"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2003.1179900"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2008.93"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/2.917534"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/IMW.2010.5488396"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1145\/1950365.1950391"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/4.799868"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/4.658627"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.13"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/16.678551"},{"key":"9","doi-asserted-by":"crossref","first-page":"82","DOI":"10.1145\/280756.280792","article-title":"Optimizing the DRAM refresh count for merged DRAM\/logic LSIs","author":"ohsawa","year":"1998","journal-title":"Proceedings 1998 International Symposium on Low Power Electronics and Design (IEEE Cat No 98TH8379) LPE"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2006.1598122"}],"event":{"name":"2013 IEEE 31st VLSI Test Symposium (VTS)","start":{"date-parts":[[2013,4,29]]},"location":"Berkeley, CA","end":{"date-parts":[[2013,5,2]]}},"container-title":["2013 IEEE 31st VLSI Test Symposium (VTS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6530960\/6548868\/06548927.pdf?arnumber=6548927","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,21]],"date-time":"2017-06-21T11:58:10Z","timestamp":1498046290000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6548927\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,4]]},"references-count":24,"URL":"https:\/\/doi.org\/10.1109\/vts.2013.6548927","relation":{},"subject":[],"published":{"date-parts":[[2013,4]]}}}