{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,21]],"date-time":"2025-05-21T22:46:05Z","timestamp":1747867565957,"version":"3.28.0"},"reference-count":29,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013,4]]},"DOI":"10.1109\/vts.2013.6548940","type":"proceedings-article","created":{"date-parts":[[2013,7,9]],"date-time":"2013-07-09T14:59:10Z","timestamp":1373381950000},"page":"1-6","source":"Crossref","is-referenced-by-count":3,"title":["Allocation of RAM built-in self-repair circuits for SOC dies of 3D ICs"],"prefix":"10.1109","author":[{"family":"Chih-Sheng Hou","sequence":"first","affiliation":[]},{"family":"Jin-Fu Li","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2061570"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2006.1594763"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2007.903940"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2017906"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2002.1181737"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2007.4"},{"key":"14","first-page":"1","article-title":"A shared parallel built-in self-repair scheme for random access memories in SOCs","author":"tseng","year":"2008","journal-title":"Proc Int'l Test Conf (ITC)"},{"key":"11","first-page":"81","article-title":"An integrated ECC and redundancy repair scheme for memory reliability enhancement","author":"su","year":"2005","journal-title":"Proc IEEE Int'l Symp on Defect and Fault Tolerance in VLSI Systems (DFT) Monterey CA"},{"key":"12","doi-asserted-by":"crossref","first-page":"742","DOI":"10.1109\/TVLSI.2005.848824","article-title":"A built-in self-repair design for RAMs with 2-D redundancies","volume":"13","author":"li","year":"2005","journal-title":"IEEE Trans on VLSI Systems"},{"key":"21","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2003.1198687"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2010.121"},{"key":"22","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2004.1387365"},{"key":"23","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2010.5469627"},{"key":"24","doi-asserted-by":"crossref","first-page":"1731","DOI":"10.1109\/TCAD.2011.2160174","article-title":"Memory built-in self-repair planning framework for RAMs in SoCs","volume":"30","author":"hou","year":"2011","journal-title":"IEEE Trans on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"25","first-page":"1277","article-title":"Challenges and emerging solutions in testing TSVbased 2 1 2D-and 3D-stacked ICs","author":"marinissen","year":"2012","journal-title":"Proc Conf Design Automation and Test in Europe (DATE)"},{"journal-title":"International Technology Roadmap for Semiconductors (ITRS) 2011 Edition","year":"2011","key":"26"},{"key":"27","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2007.26"},{"key":"28","doi-asserted-by":"publisher","DOI":"10.1109\/DELTA.2010.42"},{"key":"29","doi-asserted-by":"publisher","DOI":"10.1109\/54.199799"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2008.2007473"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2008.2007463"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2008.2007458"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.2004.1299258"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1999.805645"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1999.805644"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1998.743312"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2002.1041777"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/MTDT.2003.1222364"},{"key":"8","first-page":"366","article-title":"A processor-based built-in selfrepair design for embedded memories","author":"su","year":"2003","journal-title":"Proc 11th IEEE Asian Test Symp (ATS)"}],"event":{"name":"2013 IEEE 31st VLSI Test Symposium (VTS)","start":{"date-parts":[[2013,4,29]]},"location":"Berkeley, CA","end":{"date-parts":[[2013,5,2]]}},"container-title":["2013 IEEE 31st VLSI Test Symposium (VTS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6530960\/6548868\/06548940.pdf?arnumber=6548940","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,21]],"date-time":"2017-06-21T15:58:08Z","timestamp":1498060688000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6548940\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,4]]},"references-count":29,"URL":"https:\/\/doi.org\/10.1109\/vts.2013.6548940","relation":{},"subject":[],"published":{"date-parts":[[2013,4]]}}}