{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T09:11:56Z","timestamp":1729674716075,"version":"3.28.0"},"reference-count":38,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,4]]},"DOI":"10.1109\/vts.2014.6818773","type":"proceedings-article","created":{"date-parts":[[2014,5,30]],"date-time":"2014-05-30T18:34:07Z","timestamp":1401474847000},"page":"1-4","source":"Crossref","is-referenced-by-count":0,"title":["Unstructured text: Test analysis techniques applied to non-test problems"],"prefix":"10.1109","author":[{"given":"Anne","family":"Gattiker","sequence":"first","affiliation":[]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2005.1583979"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2012.6401595"},{"key":"35","doi-asserted-by":"publisher","DOI":"10.1002\/(SICI)1097-4571(199009)41:6<391::AID-ASI1>3.0.CO;2-9"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2012.6401547"},{"key":"36","doi-asserted-by":"crossref","first-page":"788","DOI":"10.1038\/44565","article-title":"Learning the parts of objects by non-negative matrix factorization","volume":"401","author":"lee","year":"0","journal-title":"Nature"},{"key":"15","doi-asserted-by":"crossref","DOI":"10.1109\/TVLSI.2005.863183","article-title":"Estimation of fault-free leakage current using wafer-level spat ial information","author":"sabade","year":"2006","journal-title":"IEEE Trans on Very Large Scale Integration (VLSI) Systems"},{"key":"33","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2010.5699249"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2008.4700548"},{"key":"34","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2005.1583971"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2002.1041819"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.2004.1299224"},{"key":"11","article-title":"Neighbor Selection for Variance Reduction in IDDQ and Other Parametric Data","author":"daasch","year":"2002","journal-title":"ITC"},{"year":"0","key":"37"},{"key":"12","article-title":"Statistical post-processing at wafersort-an alternative to burn-in and a manufacturable solution to test limit setting for submicron technologies","author":"madge","year":"0","journal-title":"IEEE VLSI Test Symposium 2002"},{"year":"0","author":"stewart","key":"38"},{"key":"21","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2010.5699271"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.855835"},{"key":"22","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2066630"},{"key":"23","doi-asserted-by":"publisher","DOI":"10.1145\/2429384.2429390"},{"key":"24","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2010.5699231"},{"key":"25","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2012.49"},{"key":"26","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2013.6651899"},{"key":"27","article-title":"Clustering based techniques for IDDQ testing","author":"jandhyala","year":"1999","journal-title":"ITC"},{"key":"28","article-title":"Clustering based evaluation of IDDQ measurements: Applications in testing and classification of ICs","author":"jandhyala","year":"0","journal-title":"VLSI Test Symposium 2000"},{"key":"29","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2010.5699239"},{"key":"3","article-title":"Current Measurement Data To Demonstrate Setting Current Limits in a Complete Iddq Testing Methodology","author":"acken","year":"0","journal-title":"IEEE International Workshop on Iddq Testing October 1995"},{"key":"2","article-title":"Measurements of Quiescent Power Supply Current for CMOS ICs in Production Testing","author":"horning","year":"1987","journal-title":"ITC"},{"key":"10","article-title":"Improved Wafer-Level Spatial Analysis for IDDQ Limit Setting","author":"sabade","year":"2001","journal-title":"ITC"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1017\/CBO9780511809071"},{"key":"30","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2011.6139137"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2000.894324"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.1998.741606"},{"key":"32","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2008.4700549"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/IDDQ.1997.633011"},{"key":"31","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2013.6651901"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1997.639608"},{"key":"9","article-title":"Improving Delta-IDDQ-Based Test Methods","author":"thibeault","year":"2000","journal-title":"ITC"},{"key":"8","article-title":"Multiple-Parameter CMOS IC Testing with Increased Sensitivity for IDDQ","author":"keshavarzi","year":"2000","journal-title":"ITC"}],"event":{"name":"2014 IEEE 32nd VLSI Test Symposium (VTS)","start":{"date-parts":[[2014,4,13]]},"location":"Napa, CA, USA","end":{"date-parts":[[2014,4,17]]}},"container-title":["2014 IEEE 32nd VLSI Test Symposium (VTS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6811042\/6818727\/06818773.pdf?arnumber=6818773","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,11]],"date-time":"2019-08-11T04:40:47Z","timestamp":1565498447000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6818773\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,4]]},"references-count":38,"URL":"https:\/\/doi.org\/10.1109\/vts.2014.6818773","relation":{},"subject":[],"published":{"date-parts":[[2014,4]]}}}