{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,19]],"date-time":"2026-06-19T15:49:48Z","timestamp":1781884188013,"version":"3.54.5"},"reference-count":19,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,4]]},"DOI":"10.1109\/vts.2016.7477271","type":"proceedings-article","created":{"date-parts":[[2016,5,26]],"date-time":"2016-05-26T20:27:12Z","timestamp":1464294432000},"page":"1-6","source":"Crossref","is-referenced-by-count":8,"title":["Building trust in 3PIP using asset-based security property verification"],"prefix":"10.1109","author":[{"given":"Juan","family":"Portillo","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Eugene","family":"John","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Seetharam","family":"Narasimhan","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/2508859.2516654"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488808"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/HPCC.2014.112"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2011.5954998"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2010.5513114"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2013.2247458"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/LES.2013.2261572"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/2744769.2744823"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2014.6865092"},{"key":"ref19","first-page":"1","article-title":"Formal verification of taint-ptopagation security properties in a commercial SoC design","author":"subramanyan","year":"2014","journal-title":"Design Automation and Test in Europe (DATE)"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/DFT.2013.6653605"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/MTV.2013.24"},{"key":"ref6","article-title":"Coverage analysis techniques for HDL design validation","author":"jou","year":"1999","journal-title":"IEEE Asia Pacific Conference on Chip Design Languages"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/SP.2011.27"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2010.299"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2013.6691208"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2014.2335155"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2014.2334493"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/SP.2010.18"}],"event":{"name":"2016 IEEE 34th VLSI Test Symposium (VTS)","location":"Las Vegas, NV, USA","start":{"date-parts":[[2016,4,25]]},"end":{"date-parts":[[2016,4,27]]}},"container-title":["2016 IEEE 34th VLSI Test Symposium (VTS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7469602\/7477250\/07477271.pdf?arnumber=7477271","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2016,9,23]],"date-time":"2016-09-23T20:07:17Z","timestamp":1474661237000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7477271\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,4]]},"references-count":19,"URL":"https:\/\/doi.org\/10.1109\/vts.2016.7477271","relation":{},"subject":[],"published":{"date-parts":[[2016,4]]}}}