{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,7]],"date-time":"2024-09-07T23:49:15Z","timestamp":1725752955092},"reference-count":15,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,4]]},"DOI":"10.1109\/vts.2016.7477313","type":"proceedings-article","created":{"date-parts":[[2016,5,26]],"date-time":"2016-05-26T16:27:12Z","timestamp":1464280032000},"page":"1-6","source":"Crossref","is-referenced-by-count":11,"title":["Scalable parallel fault simulation for shared-memory multiprocessor systems"],"prefix":"10.1109","author":[{"given":"Stavros","family":"Hadjitheophanous","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Stelios N.","family":"Neophytou","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Maria K.","family":"Michael","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"doi-asserted-by":"publisher","key":"ref10","DOI":"10.1109\/TCAD.2011.2158432"},{"doi-asserted-by":"publisher","key":"ref11","DOI":"10.1007\/s10836-010-5147-x"},{"doi-asserted-by":"publisher","key":"ref12","DOI":"10.1109\/TEST.2010.5699235"},{"doi-asserted-by":"publisher","key":"ref13","DOI":"10.7873\/DATE.2015.0077"},{"doi-asserted-by":"publisher","key":"ref14","DOI":"10.7873\/DATE.2015.0226"},{"doi-asserted-by":"publisher","key":"ref15","DOI":"10.1109\/DAC.1983.1585651"},{"doi-asserted-by":"publisher","key":"ref4","DOI":"10.1109\/43.57785"},{"doi-asserted-by":"publisher","key":"ref3","DOI":"10.1109\/TEST.1989.82361"},{"doi-asserted-by":"publisher","key":"ref6","DOI":"10.1145\/196244.196519"},{"doi-asserted-by":"publisher","key":"ref5","DOI":"10.1007\/BF00159833"},{"key":"ref8","article-title":"Parallel Path Delay Fault Simulation for MultilMany-Core Processors with SIMD Units","author":"yussuf","year":"2014","journal-title":"Proc of ATS"},{"doi-asserted-by":"publisher","key":"ref7","DOI":"10.1109\/92.766745"},{"year":"1994","author":"banerjee","journal-title":"Parallel Algorithms for VLSI Computer-Aided Design","key":"ref2"},{"year":"2006","author":"wang","journal-title":"VLSI Test Principles and Architectures Design for Testability","key":"ref1"},{"doi-asserted-by":"publisher","key":"ref9","DOI":"10.1145\/1837274.1837369"}],"event":{"name":"2016 IEEE 34th VLSI Test Symposium (VTS)","start":{"date-parts":[[2016,4,25]]},"location":"Las Vegas, NV, USA","end":{"date-parts":[[2016,4,27]]}},"container-title":["2016 IEEE 34th VLSI Test Symposium (VTS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7469602\/7477250\/07477313.pdf?arnumber=7477313","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2016,9,23]],"date-time":"2016-09-23T16:07:30Z","timestamp":1474646850000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7477313\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,4]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/vts.2016.7477313","relation":{},"subject":[],"published":{"date-parts":[[2016,4]]}}}