{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,19]],"date-time":"2026-06-19T15:45:09Z","timestamp":1781883909141,"version":"3.54.5"},"reference-count":9,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,4]]},"DOI":"10.1109\/vts.2017.7928922","type":"proceedings-article","created":{"date-parts":[[2017,5,18]],"date-time":"2017-05-18T22:35:20Z","timestamp":1495146920000},"page":"1-6","source":"Crossref","is-referenced-by-count":3,"title":["An optimised SDD ATPG and SDQL computation method across different pattern sets"],"prefix":"10.1109","author":[{"given":"Wilson","family":"Pradeep","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Prakash","family":"Narayanan","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Rubin","family":"Parekhji","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2011.5783759"},{"key":"ref3","year":"2015","journal-title":"Encounter Test User Guide v15 13 Cadence Design Systems"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2010.63"},{"key":"ref5","article-title":"As-Robust-As-Possible Test Generation in the Presence of Small Delay Defects using Pseudo-Boolean Optimization","author":"ggersgl","year":"2011","journal-title":"Design Autom & Test in Europe (DATE) Conf"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2009.28"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2010.5469619"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2005.1584088"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2006.261012"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2011.5783735"}],"event":{"name":"2017 IEEE 35th VLSI Test Symposium (VTS)","location":"Las Vegas, NV, USA","start":{"date-parts":[[2017,4,9]]},"end":{"date-parts":[[2017,4,12]]}},"container-title":["2017 IEEE 35th VLSI Test Symposium (VTS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7921795\/7928905\/07928922.pdf?arnumber=7928922","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,5,31]],"date-time":"2017-05-31T04:20:12Z","timestamp":1496204412000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7928922\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,4]]},"references-count":9,"URL":"https:\/\/doi.org\/10.1109\/vts.2017.7928922","relation":{},"subject":[],"published":{"date-parts":[[2017,4]]}}}