{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,21]],"date-time":"2025-06-21T04:29:45Z","timestamp":1750480185356},"reference-count":14,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,4]]},"DOI":"10.1109\/vts.2018.8368630","type":"proceedings-article","created":{"date-parts":[[2018,5,31]],"date-time":"2018-05-31T18:16:52Z","timestamp":1527790612000},"page":"1-6","source":"Crossref","is-referenced-by-count":26,"title":["Hardware Trojan attacks in embedded memory"],"prefix":"10.1109","author":[{"given":"Tamzidul","family":"Hoque","sequence":"first","affiliation":[]},{"given":"Xinmu","family":"Wang","sequence":"additional","affiliation":[]},{"given":"Abhishek","family":"Basak","sequence":"additional","affiliation":[]},{"given":"Robert","family":"Karam","sequence":"additional","affiliation":[]},{"given":"Swarup","family":"Bhunia","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","article-title":"Memory Test Experiment: Industrial Results and Data","author":"cheng","year":"2002","journal-title":"IEEE TCAD"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2002.1011170"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.826578"},{"key":"ref13","article-title":"Testing Semiconductor Memories: Theory and Practice","author":"de goor","year":"1991","journal-title":"John Wiley & Sons Inc"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/DFT.2015.7315147"},{"key":"ref4","article-title":"Golden-Free Hardware Trojan Detection with High Sensitivity Under Process Noise","author":"hoque","year":"2016","journal-title":"JETTA"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2014.2334493"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISTEL.2016.7881917"},{"key":"ref5","article-title":"Designing and Implementing Malicious Hardware","author":"king","year":"2008","journal-title":"LEET"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2010.5456930"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/DFT.2014.6962105"},{"key":"ref2","article-title":"On Design Vulnerability Analysis and Trust Benchmarks Development","author":"lovric","year":"2013","journal-title":"ICCD"},{"key":"ref1","article-title":"International Technology Roadmap for Semiconductors Explores Next 15 Years of Chip Technology","author":"rosso","year":"2014","journal-title":"International Technology Roadmap for Semiconductors"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2016.7477272"}],"event":{"name":"2018 IEEE 36th VLSI Test Symposium (VTS)","start":{"date-parts":[[2018,4,22]]},"location":"San Francisco, CA","end":{"date-parts":[[2018,4,25]]}},"container-title":["2018 IEEE 36th VLSI Test Symposium (VTS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8362837\/8368610\/08368630.pdf?arnumber=8368630","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,25]],"date-time":"2022-01-25T23:42:42Z","timestamp":1643154162000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8368630\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,4]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/vts.2018.8368630","relation":{},"subject":[],"published":{"date-parts":[[2018,4]]}}}