{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,28]],"date-time":"2025-10-28T10:49:15Z","timestamp":1761648555797},"reference-count":24,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,4]]},"DOI":"10.1109\/vts.2018.8368635","type":"proceedings-article","created":{"date-parts":[[2018,5,31]],"date-time":"2018-05-31T18:16:52Z","timestamp":1527790612000},"page":"1-6","source":"Crossref","is-referenced-by-count":9,"title":["An inter-layer interconnect BIST solution for monolithic 3D ICs"],"prefix":"10.1109","author":[{"given":"Abhishek","family":"Koneru","sequence":"first","affiliation":[]},{"given":"Krishnendu","family":"Chakrabarty","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/EPEPS.2016.7835425"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ASMC.2006.1638778"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2011.6139179"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ETS.2016.7519330"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1998.743172"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ESSDERC.2013.6818841"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/3DIC.2013.6702386"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2017.119"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2009.5355573"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/2593069.2593188"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/2717764.2717779"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488776"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/3041026"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2012.2223593"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2015.7223698"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ETS.2016.7519292"},{"key":"ref2","article-title":"Device performance analysis on 20nm technology thin wafers in a 3D package","author":"kannan","year":"2015","journal-title":"IRPS"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-22093-2_3"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1149\/06405.0381ecst"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2015.21"},{"key":"ref22","first-page":"6","article-title":"New generation of predictive technology model for sub-45nm design exploration","author":"zhao","year":"2006","journal-title":"ISQED"},{"journal-title":"Supplementary Documents","year":"0","key":"ref21"},{"key":"ref24","article-title":"Worst-case analysis of a new heuristic for the travelling salesman problem","author":"christofides","year":"1976","journal-title":"Symposium on New Directions and Recent Results in Algorithms and Complexity"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1137\/0105003"}],"event":{"name":"2018 IEEE 36th VLSI Test Symposium (VTS)","start":{"date-parts":[[2018,4,22]]},"location":"San Francisco, CA","end":{"date-parts":[[2018,4,25]]}},"container-title":["2018 IEEE 36th VLSI Test Symposium (VTS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8362837\/8368610\/08368635.pdf?arnumber=8368635","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,25]],"date-time":"2022-01-25T23:50:13Z","timestamp":1643154613000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8368635\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,4]]},"references-count":24,"URL":"https:\/\/doi.org\/10.1109\/vts.2018.8368635","relation":{},"subject":[],"published":{"date-parts":[[2018,4]]}}}