{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T03:52:01Z","timestamp":1725594721229},"reference-count":8,"publisher":"IEEE","license":[{"start":{"date-parts":[[2019,4,1]],"date-time":"2019-04-01T00:00:00Z","timestamp":1554076800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,4,1]],"date-time":"2019-04-01T00:00:00Z","timestamp":1554076800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,4,1]],"date-time":"2019-04-01T00:00:00Z","timestamp":1554076800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,4]]},"DOI":"10.1109\/vts.2019.8758603","type":"proceedings-article","created":{"date-parts":[[2019,7,11]],"date-time":"2019-07-11T23:56:14Z","timestamp":1562889374000},"page":"1-6","source":"Crossref","is-referenced-by-count":1,"title":["Silicon Proven Timing Signoff Methodology using Hazard-Free Robust Path Delay Tests"],"prefix":"10.1109","author":[{"given":"Ankit","family":"Shah","sequence":"first","affiliation":[]},{"given":"Raman","family":"Nayyar","sequence":"additional","affiliation":[]},{"given":"Arani","family":"Sinha","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ETS.2009.12"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/1837274.1837368"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/1629911.1630005"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2012.2208353"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2010.5699257"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/FMCAD.2014.6987605"},{"key":"ref2","article-title":"Path selection based on static timing analysis considering input necessary assignments","author":"yao","year":"2013","journal-title":"Proc of VLSI Test Symposium"},{"key":"ref1","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4615-5597-1","author":"krstic","year":"1998","journal-title":"Delay Fault Testing for VLSI Circuits"}],"event":{"name":"2019 IEEE 37th VLSI Test Symposium (VTS)","start":{"date-parts":[[2019,4,23]]},"location":"Monterey, CA, USA","end":{"date-parts":[[2019,4,25]]}},"container-title":["2019 IEEE 37th VLSI Test Symposium (VTS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8753115\/8758605\/08758603.pdf?arnumber=8758603","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,18]],"date-time":"2022-07-18T14:52:56Z","timestamp":1658155976000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8758603\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,4]]},"references-count":8,"URL":"https:\/\/doi.org\/10.1109\/vts.2019.8758603","relation":{},"subject":[],"published":{"date-parts":[[2019,4]]}}}