{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,7]],"date-time":"2024-09-07T15:35:48Z","timestamp":1725723348415},"reference-count":15,"publisher":"IEEE","license":[{"start":{"date-parts":[[2019,4,1]],"date-time":"2019-04-01T00:00:00Z","timestamp":1554076800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,4,1]],"date-time":"2019-04-01T00:00:00Z","timestamp":1554076800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,4,1]],"date-time":"2019-04-01T00:00:00Z","timestamp":1554076800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,4]]},"DOI":"10.1109\/vts.2019.8758644","type":"proceedings-article","created":{"date-parts":[[2019,7,11]],"date-time":"2019-07-11T23:56:14Z","timestamp":1562889374000},"page":"1-6","source":"Crossref","is-referenced-by-count":8,"title":["Test Compaction Under Bounded Transparent-Scan"],"prefix":"10.1109","author":[{"given":"Irith","family":"Pomeranz","sequence":"first","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2003.819424"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/43.238615"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/43.298042"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.884405"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cdt:20060142"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2011.5783760"},{"key":"ref4","first-page":"1128","article-title":"Test Application Time Reduction for Sequential Circuits with Scan","author":"lee","year":"1995","journal-title":"IEEE Trans on Computer-Aided Design"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2014.2358932"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2008.4700648"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/775832.776000"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2015.7116296"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2408257"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2011.5783735"},{"key":"ref1","first-page":"189","article-title":"Test Generation and Dynamic Compaction of Tests","author":"goel","year":"1979","journal-title":"Proc Test Conf"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2016.40"}],"event":{"name":"2019 IEEE 37th VLSI Test Symposium (VTS)","start":{"date-parts":[[2019,4,23]]},"location":"Monterey, CA, USA","end":{"date-parts":[[2019,4,25]]}},"container-title":["2019 IEEE 37th VLSI Test Symposium (VTS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8753115\/8758605\/08758644.pdf?arnumber=8758644","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,18]],"date-time":"2022-07-18T14:52:56Z","timestamp":1658155976000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8758644\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,4]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/vts.2019.8758644","relation":{},"subject":[],"published":{"date-parts":[[2019,4]]}}}