{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,7,14]],"date-time":"2025-07-14T02:47:24Z","timestamp":1752461244803},"reference-count":28,"publisher":"IEEE","license":[{"start":{"date-parts":[[2020,4,1]],"date-time":"2020-04-01T00:00:00Z","timestamp":1585699200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,4,1]],"date-time":"2020-04-01T00:00:00Z","timestamp":1585699200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2020,4]]},"DOI":"10.1109\/vts48691.2020.9107572","type":"proceedings-article","created":{"date-parts":[[2020,6,4]],"date-time":"2020-06-04T20:30:31Z","timestamp":1591302631000},"page":"1-6","source":"Crossref","is-referenced-by-count":4,"title":["A dynamic reconfiguration mechanism to increase the reliability of GPGPUs"],"prefix":"10.1109","author":[{"given":"Josie E.","family":"Rodriguez Condia","sequence":"first","affiliation":[{"name":"Politecnico di Torino,Torino,Italy"}]},{"given":"Pierpaolo","family":"Narducci","sequence":"additional","affiliation":[{"name":"Politecnico di Torino,Torino,Italy"}]},{"given":"M. Sonza","family":"Reorda","sequence":"additional","affiliation":[{"name":"Politecnico di Torino,Torino,Italy"}]},{"given":"L.","family":"Sterpone","sequence":"additional","affiliation":[{"name":"Politecnico di Torino,Torino,Italy"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/LATW.2019.8704560"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2014.6835966"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2013.6718353"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/2333660.2333752"},{"key":"ref14","first-page":"5","article-title":"A scalable GPU architecture based on dynamically reconfigurable embedded processor","author":"lee","year":"2011","journal-title":"High Performance Graphics"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2017.59"},{"key":"ref16","first-page":"2009","article-title":"EFECT TOLERANT REDUNDANCY","author":"nickolls","year":"0","journal-title":"patent NVIDIA Corp"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ETS.2013.6569353"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/IDT.2013.6727092"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/IOLTS.2018.8474174"},{"key":"ref28","article-title":"Nangate 45nm Open Cell Library","author":"knudsen","year":"2008","journal-title":"CDNLive! EMEA"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2010.120"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/DTIS.2019.8735047"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2013.040"},{"key":"ref6","first-page":"81","article-title":"An integrated ECC and redundancy repair scheme for memory reliability enhancement","author":"su","year":"2005","journal-title":"20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05)"},{"key":"ref5","first-page":"1","article-title":"Logic self repair based on regular building blocks","author":"koal","year":"2009","journal-title":"22th International Conference on Architecture of Computing Systems 2009"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/LATW.2016.7483336"},{"key":"ref7","first-page":"366","article-title":"A processor-based built-in self- repair design for embedded memories","author":"su","year":"2003","journal-title":"2003 Test Symposium"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2014.354"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/DDECS.2010.5491821"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2017.07.007"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/DDECS.2019.8724672"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2017.07.035"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/IOLTS.2019.8854463"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2013.6651908"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/IOLTS.2013.6604088"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2013.6718358"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/2678373.2665686"}],"event":{"name":"2020 IEEE 38th VLSI Test Symposium (VTS)","start":{"date-parts":[[2020,4,5]]},"location":"San Diego, CA, USA","end":{"date-parts":[[2020,4,8]]}},"container-title":["2020 IEEE 38th VLSI Test Symposium (VTS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9106465\/9107548\/09107572.pdf?arnumber=9107572","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,6,25]],"date-time":"2024-06-25T18:28:30Z","timestamp":1719340110000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9107572\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,4]]},"references-count":28,"URL":"https:\/\/doi.org\/10.1109\/vts48691.2020.9107572","relation":{},"subject":[],"published":{"date-parts":[[2020,4]]}}}