{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T15:55:54Z","timestamp":1730303754661,"version":"3.28.0"},"reference-count":24,"publisher":"IEEE","license":[{"start":{"date-parts":[[2020,4,1]],"date-time":"2020-04-01T00:00:00Z","timestamp":1585699200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,4,1]],"date-time":"2020-04-01T00:00:00Z","timestamp":1585699200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,4,1]],"date-time":"2020-04-01T00:00:00Z","timestamp":1585699200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2020,4]]},"DOI":"10.1109\/vts48691.2020.9107588","type":"proceedings-article","created":{"date-parts":[[2020,6,4]],"date-time":"2020-06-04T20:30:31Z","timestamp":1591302631000},"page":"1-6","source":"Crossref","is-referenced-by-count":2,"title":["Flush+Time: A High Accuracy and High Resolution Cache Attack On ARM-FPGA Embedded SoC"],"prefix":"10.1109","author":[{"given":"Churan","family":"Tang","sequence":"first","affiliation":[]},{"given":"Pengkun","family":"Liu","sequence":"additional","affiliation":[]},{"given":"Cunqing","family":"Ma","sequence":"additional","affiliation":[]},{"given":"Zongbin","family":"Liu","sequence":"additional","affiliation":[]},{"given":"Jingquan","family":"Ge","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","first-page":"56","article-title":"Improved cache trace attack on aes and clefia by considering cache miss and s-box misalignment","volume":"2010","author":"zhao","year":"2010","journal-title":"IACR Cryptology ePrint Archive"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ITCC.2005.62"},{"key":"ref12","first-page":"76","article-title":"Collision attacks on processors with cache and countermeasures","volume":"5","author":"lauradoux","year":"2005","journal-title":"WEWoRC"},{"key":"ref13","first-page":"719","article-title":"Flush+ reload: a high resolution, low noise, l3 cache side-channel attack","author":"yarom","year":"2014","journal-title":"23rd USENIX Security Symposium ( USENIX Security 14)"},{"key":"ref14","first-page":"549","article-title":"Armageddon: Cache attacks on mobile devices","author":"lipp","year":"2016","journal-title":"25th USENIX Security Symposium ( USENIX Security 16)"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-40667-1_14"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/2714576.2714625"},{"key":"ref17","first-page":"897","article-title":"Cache template attacks: Automating attacks on inclusive last-level caches","author":"gruss","year":"2015","journal-title":"24th USENIX Security Symposium USENIX Security 15"},{"article-title":"Cache missing for fun and profit","year":"2005","author":"percival","key":"ref18"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/SP.2015.43"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1007\/11605805_1"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/SP.2011.22"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-32946-3_23"},{"key":"ref5","article-title":"Theoretical use of cache memory as a cryptanalytic sidechannel","volume":"2002","author":"page","year":"2002","journal-title":"IACR Cryptology ePrint Archive"},{"key":"ref8","doi-asserted-by":"crossref","first-page":"369","DOI":"10.1145\/1128817.1128887","article-title":"A refined look at bernstein’s aes side-channel analysis","author":"neve","year":"2006","journal-title":"Proceedings of the 2006 ACM Symposium on Information computer and communications security"},{"key":"ref7","first-page":"271","article-title":"Cache based remote timing attack on the aes","author":"ac?ic\u00b8mez","year":"2007","journal-title":"The Cryptographers Track at the RSA Conference"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1007\/11894063_16"},{"key":"ref1","first-page":"8","article-title":"Timing attacks on aes","volume":"2012","author":"rijmen","year":"2012","journal-title":"Hakin9"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1007\/11935308_9"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/SP.2013.23"},{"key":"ref22","article-title":"Spectre attacks: Exploiting speculative execution","author":"kocher","year":"2018","journal-title":"arXiv preprint arXiv 1801 01000"},{"key":"ref21","article-title":"Analyzing performance vulnerability due to resource denial of service attack on chip multiprocessors","author":"woo","year":"2007","journal-title":"Workshop on Chip Multiprocessor Memory Systems and Interconnects"},{"year":"0","key":"ref24","article-title":"Arm architecture reference manual: Armv7-a and armv7r edition"},{"key":"ref23","first-page":"973","article-title":"Meltdown: Reading kernel memory from user space","author":"lipp","year":"2018","journal-title":"27th USENIX Security Symposium ( USENIX Security 18)"}],"event":{"name":"2020 IEEE 38th VLSI Test Symposium (VTS)","start":{"date-parts":[[2020,4,5]]},"location":"San Diego, CA, USA","end":{"date-parts":[[2020,4,8]]}},"container-title":["2020 IEEE 38th VLSI Test Symposium (VTS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9106465\/9107548\/09107588.pdf?arnumber=9107588","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,6,30]],"date-time":"2022-06-30T15:16:32Z","timestamp":1656602192000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9107588\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,4]]},"references-count":24,"URL":"https:\/\/doi.org\/10.1109\/vts48691.2020.9107588","relation":{},"subject":[],"published":{"date-parts":[[2020,4]]}}}