{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,7]],"date-time":"2024-09-07T13:17:43Z","timestamp":1725715063198},"reference-count":25,"publisher":"IEEE","license":[{"start":{"date-parts":[[2022,4,25]],"date-time":"2022-04-25T00:00:00Z","timestamp":1650844800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,4,25]],"date-time":"2022-04-25T00:00:00Z","timestamp":1650844800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2022,4,25]]},"DOI":"10.1109\/vts52500.2021.9794232","type":"proceedings-article","created":{"date-parts":[[2022,6,15]],"date-time":"2022-06-15T16:19:24Z","timestamp":1655309964000},"page":"1-7","source":"Crossref","is-referenced-by-count":5,"title":["Fast Test Generation for Structurally Similar Circuits"],"prefix":"10.1109","author":[{"given":"Jerin","family":"Joe","sequence":"first","affiliation":[{"name":"Purdue University,School of Electrical &amp; Computer Engg.,W. Lafayette,IN,USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Nilanjan","family":"Mukherjee","sequence":"additional","affiliation":[{"name":"Siemens Digital Industries Software,Wilsonville,OR,USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Irith","family":"Pomeranz","sequence":"additional","affiliation":[{"name":"Purdue University,School of Electrical &amp; Computer Engg.,W. Lafayette,IN,USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Janusz","family":"Rajski","sequence":"additional","affiliation":[{"name":"Siemens Digital Industries Software,Wilsonville,OR,USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ITC-Asia.2019.00024"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCS.1979.1084687"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2014.32"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ETS.2014.6847839"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2019.8758655"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2011.6139171"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1986.1586119"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.1991.139840"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1994.629736"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/217474.217604"},{"key":"ref4","first-page":"1213","article-title":"GPU Accelerated VLSI Design Verification","author":"deng","year":"2010","journal-title":"IEEE International Conference on Computer and Information Technology"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/2.803642"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2013.209"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2004.1261846"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/VLSI-DAT.2016.7482582"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2003.1232252"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/1629911.1629940"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2013.45"},{"key":"ref1","first-page":"8","article-title":"Moore&#x2019;s law: A path going forward","author":"holt","year":"2016","journal-title":"International Symposium on VLSI Design Automation and Test (VLSI-DAT)"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-95432-0_7"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.1993.313353"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1007\/BF01759032"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1993.580075"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2013.6523635"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.23919\/DATE48585.2020.9116504"}],"event":{"name":"2022 IEEE 40th VLSI Test Symposium (VTS)","start":{"date-parts":[[2022,4,25]]},"location":"San Diego, CA, USA","end":{"date-parts":[[2022,4,27]]}},"container-title":["2022 IEEE 40th VLSI Test Symposium (VTS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9793839\/9794139\/09794232.pdf?arnumber=9794232","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,11]],"date-time":"2022-07-11T16:04:36Z","timestamp":1657555476000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9794232\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,4,25]]},"references-count":25,"URL":"https:\/\/doi.org\/10.1109\/vts52500.2021.9794232","relation":{},"subject":[],"published":{"date-parts":[[2022,4,25]]}}}