{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T02:57:59Z","timestamp":1725591479597},"reference-count":9,"publisher":"IEEE","license":[{"start":{"date-parts":[[2022,4,25]],"date-time":"2022-04-25T00:00:00Z","timestamp":1650844800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,4,25]],"date-time":"2022-04-25T00:00:00Z","timestamp":1650844800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2022,4,25]]},"DOI":"10.1109\/vts52500.2021.9794251","type":"proceedings-article","created":{"date-parts":[[2022,6,15]],"date-time":"2022-06-15T20:19:24Z","timestamp":1655324364000},"page":"1-6","source":"Crossref","is-referenced-by-count":0,"title":["On-Die Noise Measurement During Automatic Test Equipment (ATE) Testing and In-System-Test (IST)"],"prefix":"10.1109","author":[{"given":"Seyed Nima","family":"Mozaffari","sequence":"first","affiliation":[{"name":"NVIDIA Corporation,Santa Clara,USA"}]},{"given":"Bonita","family":"Bhaskaran","sequence":"additional","affiliation":[{"name":"NVIDIA Corporation,Santa Clara,USA"}]},{"given":"Shantanu","family":"Sarangi","sequence":"additional","affiliation":[{"name":"NVIDIA Corporation,Santa Clara,USA"}]},{"given":"Suhas","family":"Satheesh","sequence":"additional","affiliation":[{"name":"NVIDIA Corporation,Santa Clara,USA"}]},{"given":"Kuo Lin","family":"Fu","sequence":"additional","affiliation":[{"name":"NVIDIA Corporation,Taipei City,Taiwan"}]},{"given":"Nithin","family":"Valentine","sequence":"additional","affiliation":[{"name":"NVIDIA Corporation,Santa Clara,USA"}]},{"given":"P","family":"Manikandan","sequence":"additional","affiliation":[{"name":"NVIDIA Corporation,Bengaluru,India"}]},{"given":"Mahmut","family":"Yilmaz","sequence":"additional","affiliation":[{"name":"NVIDIA Corporation,Santa Clara,USA"}]}],"member":"263","reference":[{"key":"ref4","first-page":"1","article-title":"Test Method and Scheme for Low-Power Validation in Moder SOC Integrated Circuts","author":"bhaskaran","year":"2016","journal-title":"2016 IEEE 34th VLSI Test Symposium (VTS) VTS"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2016.7477290"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/SOCC.2014.6948960"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.842853"},{"key":"ref8","first-page":"1","article-title":"In-System-Test Architecture for NVIDIA Drive-AGX Platforms","author":"jagannadha","year":"2019","journal-title":"VLSI Test Symposium (VTS) 2019 IEEE 37th"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/2627369.2627656"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2016.7477289"},{"year":"0","key":"ref9"},{"key":"ref1","first-page":"1","article-title":"A Clock-gating Based Capture Power Droop Reduction Methodology for At-Speed Scan Testing","author":"yang","year":"2011","journal-title":"Design Automation and Test in Europe (DATE) 2011"}],"event":{"name":"2022 IEEE 40th VLSI Test Symposium (VTS)","start":{"date-parts":[[2022,4,25]]},"location":"San Diego, CA, USA","end":{"date-parts":[[2022,4,27]]}},"container-title":["2022 IEEE 40th VLSI Test Symposium (VTS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9793839\/9794139\/09794251.pdf?arnumber=9794251","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,11]],"date-time":"2022-07-11T20:04:44Z","timestamp":1657569884000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9794251\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,4,25]]},"references-count":9,"URL":"https:\/\/doi.org\/10.1109\/vts52500.2021.9794251","relation":{},"subject":[],"published":{"date-parts":[[2022,4,25]]}}}