{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,19]],"date-time":"2026-06-19T05:52:48Z","timestamp":1781848368510,"version":"3.54.5"},"reference-count":44,"publisher":"IEEE","license":[{"start":{"date-parts":[[2026,4,27]],"date-time":"2026-04-27T00:00:00Z","timestamp":1777248000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2026,4,27]],"date-time":"2026-04-27T00:00:00Z","timestamp":1777248000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100000028","name":"Semiconductor Research Corporation","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100000028","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2026,4,27]]},"DOI":"10.1109\/vts69484.2026.11563200","type":"proceedings-article","created":{"date-parts":[[2026,6,18]],"date-time":"2026-06-18T20:06:49Z","timestamp":1781813209000},"page":"1-7","source":"Crossref","is-referenced-by-count":0,"title":["LEAD: Link Exploitability Analysis for Die-to-Die Interconnects in Heterogeneous Integration\n                    <sup>*<\/sup>"],"prefix":"10.1109","author":[{"given":"Arjun","family":"Hati","sequence":"first","affiliation":[{"name":"Arizona State University,School of Electrical, Computer and Energy Engineering,Tempe,AZ"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Eduardo","family":"Ortega","sequence":"additional","affiliation":[{"name":"Arizona State University,School of Electrical, Computer and Energy Engineering,Tempe,AZ"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jonti","family":"Talukdar","sequence":"additional","affiliation":[{"name":"Arizona State University,School of Electrical, Computer and Energy Engineering,Tempe,AZ"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jim","family":"Plusquellic","sequence":"additional","affiliation":[{"name":"University of New Mexico,Electrical and Computer Engineering Department,Albuquerque,NM"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Krishnendu","family":"Chakrabarty","sequence":"additional","affiliation":[{"name":"Arizona State University,School of Electrical, Computer and Energy Engineering,Tempe,AZ"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","first-page":"15","article-title":"Chiplet-based architectures: Redefining the future of system-on-chip (SoC) design","volume":"17","author":"Mohammed","year":"2025","journal-title":"International Journal of Communication Networks and Information Security (IJCNIS)"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1016\/j.fmre.2023.10.020"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/3489517.3530428"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/SLIP.2019.8771333"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/MSSC.2021.3111386"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ASP-DAC58780.2024.10473961"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.23919\/ICEP.2017.7939429"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/HCS49909.2020.9220622"},{"key":"ref9","article-title":"Behind intel\u2019s HPC chip that will pierce the exascale barrier","author":"Moore","year":"2022","journal-title":"IEEE Spectrum"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC49657.2024.10454441"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/OJSSCS.2024.3506694"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2023.3340798"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED54688.2022.9806155"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/MDTS64924.2025.11177065"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1007\/s42979-020-00220-0"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2024.3368152"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TETC.2020.2984162"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2023.3248269"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/3DIC48104.2019.9058884"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/VLSITechnologyandCir46783.2024.10631545"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC19947.2020.9062957"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/HOST64725.2025.11050057"},{"key":"ref23","first-page":"2022\/984","article-title":"ToSHI - towards secure heterogeneous integration: Security risks, threat assessment, and assurance","author":"Vashistha","year":"2022","journal-title":"Cryptology ePrint Archive"},{"key":"ref24","first-page":"288","article-title":"3D execution monitor (3D-EM): Using 3D circuits to detect hardware malicious inclusions in general purpose processors","volume-title":"Proceedings of the 6th International Conference on Information Warfare and Security","author":"Bilzor"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TETC.2019.2933572"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2020.3029339"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2898104"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/AsianHOST.2016.7835561"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2013.261"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/PAINE62042.2024.10792768"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2020.3020777"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1145\/3716368.3735248"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2024.3451532"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS61496.2024.10848977"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2017.8050827"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/iolts.2016.7604700"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2025.3525903"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/ICCE-Berlin56473.2022.9937099"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2023.3280134"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/ICCIT48885.2019.9038608"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2018.8342270"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1007\/978-981-99-4752-2_6"},{"key":"ref43","article-title":"Benchmarking at the frontier of hardware security: Lessons from logic locking","author":"Tan","year":"2020","journal-title":"arXiv preprint arXiv:2006.06806"},{"key":"ref44","first-page":"5809","article-title":"FuncTeller: How well does eFPGA hide functionality?","volume-title":"USENIX Security Symposium","author":"Han"}],"event":{"name":"2026 IEEE 44th VLSI Test Symposium (VTS)","location":"Napa, CA, USA","start":{"date-parts":[[2026,4,27]]},"end":{"date-parts":[[2026,4,29]]}},"container-title":["2026 IEEE 44th VLSI Test Symposium (VTS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11563061\/11563198\/11563200.pdf?arnumber=11563200","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,6,19]],"date-time":"2026-06-19T05:27:01Z","timestamp":1781846821000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11563200\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,4,27]]},"references-count":44,"URL":"https:\/\/doi.org\/10.1109\/vts69484.2026.11563200","relation":{},"subject":[],"published":{"date-parts":[[2026,4,27]]}}}