{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T16:10:35Z","timestamp":1730304635807,"version":"3.28.0"},"reference-count":10,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,3]]},"DOI":"10.1109\/wcnc.2017.7925579","type":"proceedings-article","created":{"date-parts":[[2017,5,12]],"date-time":"2017-05-12T21:39:45Z","timestamp":1494625185000},"page":"1-5","source":"Crossref","is-referenced-by-count":1,"title":["Novel Fractional Spur Relocation in All Digital Phase Locked Loops"],"prefix":"10.1109","author":[{"given":"Basak","family":"Can","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Balvinder S.","family":"Bisla","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Satwik","family":"Patnaik","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Anthony","family":"Tsangaropoulos","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","article-title":"Analysis of Fractional Spur Reduction using ??-noise Cancellation in Digital-PLL","author":"vengattaramane","year":"2009","journal-title":"IEEE International Symposium on Circuits and Systems"},{"journal-title":"Spur Reduction Techniques for Fractional-N PLLs","year":"2010","author":"wang","key":"ref3"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/CQR.2016.7501416"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/1077603.1077658"},{"key":"ref5","article-title":"A Low Phase Noise Injection-Locked Programmable Reference Clock Multiplier With a Two-Phase PVT-Calibrator for PLLs","volume":"62","author":"lee","year":"2015","journal-title":"IEEE Transactions on Circuits and Systems"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TMTT.2009.2014431"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2077370"},{"key":"ref2","article-title":"Fractional-N Phase-Locked-Loop-Based Frequency Synthesis: A Tutorial","volume":"56","author":"su","year":"2009","journal-title":"IEEE Transactions on Circuits and Systems"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2301764"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1002\/0470041951"}],"event":{"name":"2017 IEEE Wireless Communications and Networking Conference (WCNC)","start":{"date-parts":[[2017,3,19]]},"location":"San Francisco, CA, USA","end":{"date-parts":[[2017,3,22]]}},"container-title":["2017 IEEE Wireless Communications and Networking Conference (WCNC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7924448\/7925429\/07925579.pdf?arnumber=7925579","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,5,31]],"date-time":"2017-05-31T04:26:27Z","timestamp":1496204787000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7925579\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,3]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/wcnc.2017.7925579","relation":{},"subject":[],"published":{"date-parts":[[2017,3]]}}}