{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T15:18:28Z","timestamp":1725463108484},"reference-count":15,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2009,3]]},"DOI":"10.1109\/weah.2009.4925668","type":"proceedings-article","created":{"date-parts":[[2009,5,19]],"date-time":"2009-05-19T15:54:49Z","timestamp":1242748489000},"page":"54-58","source":"Crossref","is-referenced-by-count":3,"title":["Is it time to stop evolving digital systems?"],"prefix":"10.1109","author":[{"given":"Garrison W.","family":"Greenwood","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"15","doi-asserted-by":"crossref","first-page":"55","DOI":"10.1007\/3-540-63173-9_38","article-title":"promises and challenges of evolvable hardware","author":"yao","year":"1997","journal-title":"Lecture Notes in Computer Science"},{"year":"2005","author":"wakerly","journal-title":"Digital Design Principles and Practices","key":"13"},{"key":"14","first-page":"308","article-title":"evolving variability-tolerant cmos designs","author":"walker","year":"2008","journal-title":"Proc Int Conf Evol Syst"},{"key":"11","first-page":"56","article-title":"evolving hardware by dynamically reconfiguration xilinx fpgas","author":"upegui","year":"2005","journal-title":"Proc Int Conf Evol Syst"},{"doi-asserted-by":"publisher","key":"12","DOI":"10.1109\/EH.2000.869342"},{"year":"2008","journal-title":"Xilinx Adv Product Spec DS100 v4 3","article-title":"virtex-5 family overview","key":"3"},{"year":"2003","journal-title":"Xilinx Appl Note XAPP465 v1 0","article-title":"using look-up tables as shift registers (srl16) in spartan-3 devices","key":"2"},{"year":"0","journal-title":"See","key":"1"},{"doi-asserted-by":"publisher","key":"10","DOI":"10.1109\/EH.2002.1029865"},{"key":"7","first-page":"128","article-title":"shrinking the genotype: lsystems for ehw","author":"haddow","year":"2001","journal-title":"Proc Int Conf Evol Syst"},{"key":"6","article-title":"power reduction through rtl clock gating","author":"emnett","year":"2000","journal-title":"Proc Synopsys Users Group Conf"},{"doi-asserted-by":"publisher","key":"5","DOI":"10.1109\/AHS.2007.52"},{"year":"2005","journal-title":"Precision Synthesis Product Overview","key":"4"},{"year":"2003","author":"palnitkar","journal-title":"Verilog HDL A Guide to Digital Design and Synthesis","key":"9"},{"key":"8","first-page":"145","author":"lee","year":"2005","journal-title":"Issues in the Scalability of Gate-Level Morphogenetic Evolvable Hardware"}],"event":{"name":"2009 IEEE Workshop on Evolvable and Adaptive Hardware (WEAH)","start":{"date-parts":[[2009,4,30]]},"location":"Nashville, TN, USA","end":{"date-parts":[[2009,3,2]]}},"container-title":["2009 IEEE Workshop on Evolvable and Adaptive Hardware"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4911282\/4925656\/04925668.pdf?arnumber=4925668","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,18]],"date-time":"2017-06-18T16:02:38Z","timestamp":1497801758000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4925668\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,3]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/weah.2009.4925668","relation":{},"subject":[],"published":{"date-parts":[[2009,3]]}}}