{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,3]],"date-time":"2025-10-03T13:03:24Z","timestamp":1759496604931,"version":"3.37.3"},"reference-count":46,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","license":[{"start":{"date-parts":[[2020,1,1]],"date-time":"2020-01-01T00:00:00Z","timestamp":1577836800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/legalcode"}],"funder":[{"DOI":"10.13039\/501100001871","name":"Fundao para a Cincia e a Tecnologia","doi-asserted-by":"publisher","award":["IPL\/IDI&CA\/2019\/inCNeuralN\/ISEL","PTDC\/EEI-HAC\/31819\/2017","UID\/CEC\/50021\/2019","UIDB\/50021\/2020"],"award-info":[{"award-number":["IPL\/IDI&CA\/2019\/inCNeuralN\/ISEL","PTDC\/EEI-HAC\/31819\/2017","UID\/CEC\/50021\/2019","UIDB\/50021\/2020"]}],"id":[{"id":"10.13039\/501100001871","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Access"],"published-print":{"date-parts":[[2020]]},"DOI":"10.1109\/access.2020.3000444","type":"journal-article","created":{"date-parts":[[2020,6,8]],"date-time":"2020-06-08T21:26:21Z","timestamp":1591651581000},"page":"107229-107243","source":"Crossref","is-referenced-by-count":12,"title":["A Configurable Architecture for Running Hybrid Convolutional Neural Networks in Low-Density FPGAs"],"prefix":"10.1109","volume":"8","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-8556-4507","authenticated-orcid":false,"given":"Mario P.","family":"Vestias","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7060-4745","authenticated-orcid":false,"given":"Rui P.","family":"Duarte","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7525-7546","authenticated-orcid":false,"given":"Jose T.","family":"De Sousa","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3621-8322","authenticated-orcid":false,"given":"Horacio C.","family":"Neto","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.3390\/computers5040020"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/JRPROC.1961.287779"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1145\/3020078.3021744"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2019.00062"},{"key":"ref31","first-page":"8612","article-title":"HAQ: Hardware-aware automated quantization with mixed precision","author":"wang","year":"2018","journal-title":"Proc CVPR"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2019.2913958"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.3390\/electronics8111321"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2019.00102"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2705069"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1016\/j.neucom.2017.09.046"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2016.90"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1145\/2647868.2654889"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.3390\/a12080154"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPSW.2019.00026"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TMSCS.2018.2886266"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/3020078.3021698"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TNNLS.2018.2844093"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2019.2939726"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815993"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.58"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/2847263.2847265"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2018.2857078"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ICFPT47387.2019.00014"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080221"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2018.00035"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/35.41400"},{"key":"ref29","first-page":"1","article-title":"Hardware-oriented approximation of convolutional neural networks","author":"gysel","year":"2016","journal-title":"Proc Int Conf Learn Represent"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2018.00075"},{"key":"ref8","article-title":"Very deep convolutional networks for large-scale image recognition","author":"simonyan","year":"2015","journal-title":"Proc 3rd Int Conf Learn Represent"},{"key":"ref7","first-page":"1097","article-title":"ImageNet classification with deep convolutional neural networks","volume":"1","author":"krizhevsky","year":"2012","journal-title":"Proc 25th Int Conf Neural Inf Process Syst (NIPS)"},{"key":"ref2","first-page":"23","author":"v\u00e9stias","year":"2020","journal-title":"Deep Learning on Edge Challanges and Trends"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2015.7298594"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1007\/s11263-015-0816-y"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1145\/3240765.3240801"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/2847263.2847276"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2017.2767204"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2019.2919527"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1002\/cpe.3850"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2016.22"},{"key":"ref24","first-page":"401","author":"peres","year":"2019","journal-title":"Faster Convolutional Neural Networks in Low Density FPGAs Using Block Pruning"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2009.5206848"},{"key":"ref23","first-page":"387","author":"gon\u00e7alves","year":"2019","journal-title":"Exploring Data Size to Run Convolutional Neural Networks in Low Density FPGAs"},{"key":"ref44","first-page":"155","article-title":"CascadêNN: Pushing the performance limits of quantisation in convolutional neural networks","author":"kouris","year":"2018","journal-title":"Proc Int Conf Field Program Logic Appl (FPL)"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2019.2905242"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1145\/3020078.3021741"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/3079758"}],"container-title":["IEEE Access"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6287639\/8948470\/09110581.pdf?arnumber=9110581","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,12,17]],"date-time":"2021-12-17T19:52:32Z","timestamp":1639770752000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9110581\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020]]},"references-count":46,"URL":"https:\/\/doi.org\/10.1109\/access.2020.3000444","relation":{},"ISSN":["2169-3536"],"issn-type":[{"type":"electronic","value":"2169-3536"}],"subject":[],"published":{"date-parts":[[2020]]}}}