{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,26]],"date-time":"2026-02-26T15:43:46Z","timestamp":1772120626540,"version":"3.50.1"},"reference-count":17,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/date.2004.1268845","type":"proceedings-article","created":{"date-parts":[[2004,6,21]],"date-time":"2004-06-21T21:52:40Z","timestamp":1087854760000},"page":"176-181","source":"Crossref","is-referenced-by-count":8,"title":["A probabilistic method for the computation of testability of RTL constructs"],"prefix":"10.1109","author":[{"given":"J.M.","family":"Fernandes","sequence":"first","affiliation":[]},{"given":"M.B.","family":"Santos","sequence":"additional","affiliation":[]},{"given":"A.L.","family":"Oliveira","sequence":"additional","affiliation":[]},{"given":"J.C.","family":"Teixeira","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"17","year":"1999","journal-title":"IEEE Standard P1364 1\/D1 4 \"draft Standard for Verilog Register Transfer Level Synthesis"},{"key":"15","year":"0","journal-title":"CMUDSP Benchmark"},{"key":"16","year":"1996","journal-title":"IEEE Standard Hardware Description Language Based on the Verilog Hardware Description Language"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2001.955007"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/92.406998"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2003.1253734"},{"key":"12","author":"sentovich","year":"1992","journal-title":"SIS A System for Sequential Circuits Syn Thesis\" Electronics Research Laboratory"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1145\/277044.277078"},{"key":"2","first-page":"968","article-title":"B-Algorithm: A behavioral test generation algorithm","author":"cho","year":"1994","journal-title":"Proc IEEE International Test Conference (ITC)"},{"key":"1","article-title":"Compiling verilog into automata","author":"cheng","year":"1994","journal-title":"Department of electrical engineering and computer science"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1145\/307988.307989"},{"key":"7","first-page":"239","article-title":"On the complexity of power estimation problems","author":"freitas","year":"2000","journal-title":"International Workshop on Logic Synthesis (ILWS)"},{"key":"6","first-page":"403","article-title":"Functional test generation for behaviorally sequential models","author":"ferrara","year":"2001","journal-title":"Proc of the Design Automation and Test in Europe Conference (DATE)"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1998.743202"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1999.782026"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/43.552081"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2003.1253699"}],"event":{"name":". Design, Automation and Test in Europe Conference and Exhibition","location":"Paris, France","acronym":"DATE-04"},"container-title":["Proceedings Design, Automation and Test in Europe Conference and Exhibition"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8959\/28390\/01268845.pdf?arnumber=1268845","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,14]],"date-time":"2017-03-14T01:08:39Z","timestamp":1489453719000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1268845\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":17,"URL":"https:\/\/doi.org\/10.1109\/date.2004.1268845","relation":{},"subject":[]}}