{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,18]],"date-time":"2025-06-18T04:44:17Z","timestamp":1750221857811},"reference-count":30,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,11]]},"DOI":"10.1109\/dcis.2015.7388590","type":"proceedings-article","created":{"date-parts":[[2016,1,21]],"date-time":"2016-01-21T18:13:43Z","timestamp":1453400023000},"page":"1-6","source":"Crossref","is-referenced-by-count":4,"title":["Fast radiation monitoring in FPGA-based designs"],"prefix":"10.1109","author":[{"given":"C.","family":"Leong","sequence":"first","affiliation":[]},{"given":"J.","family":"Semiao","sequence":"additional","affiliation":[]},{"given":"M.B.","family":"Santos","sequence":"additional","affiliation":[]},{"given":"I.C.","family":"Teixeira","sequence":"additional","affiliation":[]},{"given":"J.P.","family":"Teixeira","sequence":"additional","affiliation":[]},{"given":"A.J.N","family":"Batista","sequence":"additional","affiliation":[]},{"given":"B.","family":"Goncalves","sequence":"additional","affiliation":[]},{"given":"J.G.","family":"Marques","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"doi-asserted-by":"publisher","key":"ref30","DOI":"10.1109\/FPL.2011.66"},{"doi-asserted-by":"publisher","key":"ref10","DOI":"10.1109\/TNS.2006.874841"},{"doi-asserted-by":"publisher","key":"ref11","DOI":"10.1109\/FPL.2010.88"},{"doi-asserted-by":"publisher","key":"ref12","DOI":"10.1109\/FPT.2005.1568543"},{"doi-asserted-by":"publisher","key":"ref13","DOI":"10.1109\/FPL.2013.6645596"},{"doi-asserted-by":"publisher","key":"ref14","DOI":"10.1109\/ICCAD.2004.1382552"},{"doi-asserted-by":"publisher","key":"ref15","DOI":"10.1145\/1046192.1046212"},{"key":"ref16","article-title":"Single-Event Effects in 28 Nanometer Configuration and Dual-Port RAM Block Memories","author":"lesea","year":"2012","journal-title":"IEEE Silicon Errors in Logic - System Effects (SELSE)"},{"doi-asserted-by":"publisher","key":"ref17","DOI":"10.1109\/ICICDT.2011.5783237"},{"doi-asserted-by":"publisher","key":"ref18","DOI":"10.1007\/3-540-46117-5_63"},{"doi-asserted-by":"publisher","key":"ref19","DOI":"10.1016\/j.mejo.2010.06.002"},{"year":"0","key":"ref28"},{"doi-asserted-by":"publisher","key":"ref4","DOI":"10.1007\/s10836-012-5297-0"},{"doi-asserted-by":"publisher","key":"ref27","DOI":"10.1109\/FPL.2008.4629973"},{"doi-asserted-by":"publisher","key":"ref3","DOI":"10.1109\/TDSC.2007.70235"},{"doi-asserted-by":"publisher","key":"ref6","DOI":"10.1109\/DATE.2005.229"},{"doi-asserted-by":"publisher","key":"ref29","DOI":"10.1109\/TNS.2006.885952"},{"doi-asserted-by":"publisher","key":"ref5","DOI":"10.1145\/1723112.1723153"},{"doi-asserted-by":"publisher","key":"ref8","DOI":"10.1109\/MDT.2012.2206009"},{"doi-asserted-by":"publisher","key":"ref7","DOI":"10.1109\/DFT.2011.45"},{"doi-asserted-by":"publisher","key":"ref2","DOI":"10.1109\/JETCAS.2011.2135630"},{"doi-asserted-by":"publisher","key":"ref9","DOI":"10.1109\/TCSII.2010.2067810"},{"doi-asserted-by":"publisher","key":"ref1","DOI":"10.1109\/JETCAS.2011.2138250"},{"year":"2014","journal-title":"UG116 - Xilinx's Device Reliability Report","key":"ref20"},{"doi-asserted-by":"publisher","key":"ref22","DOI":"10.1016\/j.fusengdes.2012.05.005"},{"doi-asserted-by":"publisher","key":"ref21","DOI":"10.1016\/j.apradiso.2010.10.016"},{"year":"0","key":"ref24"},{"key":"ref23","article-title":"The Impact of New Technology on Soft Error Rates","author":"dixit","year":"2010","journal-title":"IEEE Silicon Errors in Logic - System Effects (SELSE)"},{"key":"ref26","article-title":"SEU Strategies for Virtex-5 Devices","author":"chapman","year":"2010","journal-title":"Xilinx&#x2122; Application Note"},{"doi-asserted-by":"publisher","key":"ref25","DOI":"10.1109\/VTS.2011.5783782"}],"event":{"name":"2015 Conference on Design of Circuits and Integrated Systems (DCIS)","start":{"date-parts":[[2015,11,25]]},"location":"Estoril, Portugal","end":{"date-parts":[[2015,11,27]]}},"container-title":["2015 Conference on Design of Circuits and Integrated Systems (DCIS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7383376\/7388553\/07388590.pdf?arnumber=7388590","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,24]],"date-time":"2017-03-24T23:48:30Z","timestamp":1490399310000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7388590\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,11]]},"references-count":30,"URL":"https:\/\/doi.org\/10.1109\/dcis.2015.7388590","relation":{},"subject":[],"published":{"date-parts":[[2015,11]]}}}