{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,7]],"date-time":"2026-01-07T22:06:17Z","timestamp":1767823577638,"version":"3.49.0"},"reference-count":11,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2003]]},"DOI":"10.1109\/dsd.2003.1231911","type":"proceedings-article","created":{"date-parts":[[2004,3,22]],"date-time":"2004-03-22T14:34:28Z","timestamp":1079966068000},"page":"128-135","source":"Crossref","is-referenced-by-count":57,"title":["RDSP: a RISC DSP based on residue number system"],"prefix":"10.1109","author":[{"given":"R.","family":"Chaves","sequence":"first","affiliation":[]},{"given":"L.","family":"Sousa","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","author":"hennessy","year":"2002","journal-title":"Computer Architecture A Quantitative Approach"},{"key":"ref3","article-title":"RDSP: A digital signal processor with suport for residue arithmetic","author":"chaves","year":"2003"},{"key":"ref10","author":"zimmermann","year":"1997","journal-title":"Binary Adder Architectures for Cellbased VLSI and Synthesis"},{"key":"ref6","article-title":"An RNS converter in 2n+ 1, 2n, 2n&#x2013; 1 moduli set","volume":"39","author":"premkumar","year":"1992","journal-title":"IEEE Transations on Circuits and Systems-II Analog and Digital Signal Processing"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ARITH.1999.762841"},{"key":"ref5","article-title":"A simplified architecture for modulo (2n+ 1) multiplication","volume":"47","author":"ma","year":"1998","journal-title":"IEEE Transactions on Computers"},{"key":"ref8","author":"soderstrand","year":"1986","journal-title":"Residue Number System Arithmetic Modern Applications in Digital Signal Processing"},{"key":"ref7","article-title":"FPL implementation of a SIMD RISC RNS-enabled DSP","author":"ramrez","year":"2000","journal-title":"Proc of the 4th World Multiconference on Circuits Systems Communications and Computers"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1016\/0165-1684(95)00092-2"},{"key":"ref9","doi-asserted-by":"crossref","DOI":"10.1007\/BF00929618","article-title":"An efficient tree architecture for modulo 2n+ 1 multiplication","author":"wang","year":"1996","journal-title":"Journal of VLSI Signal Processing"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/31.14470"}],"event":{"name":"Proceedings. Euromicro Symposium on Digital System Design","location":"Belek-Antalya, Turkey","start":{"date-parts":[[2003,9,1]]},"end":{"date-parts":[[2003,9,6]]}},"container-title":["Euromicro Symposium on Digital System Design, 2003. Proceedings."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8715\/27588\/01231911.pdf?arnumber=1231911","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,16]],"date-time":"2017-06-16T04:26:33Z","timestamp":1497587193000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1231911\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2003]]},"references-count":11,"URL":"https:\/\/doi.org\/10.1109\/dsd.2003.1231911","relation":{},"subject":[],"published":{"date-parts":[[2003]]}}}