{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T19:58:55Z","timestamp":1725652735248},"reference-count":15,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2009,8]]},"DOI":"10.1109\/fpl.2009.5272485","type":"proceedings-article","created":{"date-parts":[[2009,9,30]],"date-time":"2009-09-30T18:42:09Z","timestamp":1254336129000},"page":"457-461","source":"Crossref","is-referenced-by-count":4,"title":["Automatic generation of FPGA hardware accelerators using a domain specific language"],"prefix":"10.1109","author":[{"given":"Ricardo","family":"Menotti","sequence":"first","affiliation":[]},{"given":"Joao M. P.","family":"Cardoso","sequence":"additional","affiliation":[]},{"given":"Marcio M.","family":"Fernandes","sequence":"additional","affiliation":[]},{"given":"Eduardo","family":"Marques","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"journal-title":"Graphviz - Graph Visualization Software","year":"2006","key":"15"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2007.16"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2007.4380699"},{"journal-title":"Nios II C2H compiler user guide","year":"2008","key":"11"},{"key":"12","doi-asserted-by":"crossref","first-page":"106","DOI":"10.1145\/1062261.1062283","article-title":"dynamic loop pipelining in data-driven architectures","author":"cardoso","year":"2005","journal-title":"CF '05 Proceedings of the 2nd conference on Computing frontiers"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1145\/212094.212131"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2006.134"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2006.112"},{"journal-title":"Spark A Parallelizing Approach to the High-Level Synthesis of Digital Circuits","year":"2004","author":"gupta","key":"10"},{"key":"7","article-title":"impact of loop unrolling on area, throughput and clock frequency in roccc: c to vhdl compiler for fpgas","author":"buyukkurt","year":"2006","journal-title":"Proceedings of the International Workshop on Applied Recon gurable Computing"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2001.968639"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/2.839323"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1145\/192724.192731"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/43.908452"},{"key":"8","first-page":"221","article-title":"perfect pipelining: a new loop parallelization technique","author":"aiken","year":"1988","journal-title":"ESOP '88 Proceedings of the 2nd European Symposium on Programming"}],"event":{"name":"2009 International Conference on Field Programmable Logic and Applications (FPL)","start":{"date-parts":[[2009,8,31]]},"location":"Prague, Czech Republic","end":{"date-parts":[[2009,9,2]]}},"container-title":["2009 International Conference on Field Programmable Logic and Applications"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5247666\/5272229\/05272485.pdf?arnumber=5272485","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,19]],"date-time":"2017-06-19T00:17:20Z","timestamp":1497831440000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5272485\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,8]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/fpl.2009.5272485","relation":{},"subject":[],"published":{"date-parts":[[2009,8]]}}}