{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T02:56:51Z","timestamp":1730257011832,"version":"3.28.0"},"reference-count":12,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2008,11]]},"DOI":"10.1109\/icscs.2008.4746936","type":"proceedings-article","created":{"date-parts":[[2009,1,16]],"date-time":"2009-01-16T10:30:24Z","timestamp":1232101824000},"page":"1-6","source":"Crossref","is-referenced-by-count":3,"title":["Efficient dedicated multiplication blocks for 2’s complement radix-16 and radix-256 array multipliers"],"prefix":"10.1109","author":[{"given":"Leandro Zafalon","family":"Pieper","sequence":"first","affiliation":[]},{"given":"Eduardo A. C.","family":"da Costa","sequence":"additional","affiliation":[]},{"given":"Sergio","family":"Bampi","sequence":"additional","affiliation":[]},{"given":"Jose C.","family":"Monteiro","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"3","first-page":"345","article-title":"design and implementation of a 16 by 16 low-power 2's complekment multiplier","author":"goldovsky","year":"2000","journal-title":"IEEE ISCAS"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/ACSSC.1994.471512"},{"key":"10","first-page":"53","article-title":"a hybrid radix-4\/radix-8 low power, high speed multiplier architecture for wide bit widths","volume":"4","author":"cherkauer","year":"1996","journal-title":"IEEE ISCAS"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/PGEC.1964.263830"},{"journal-title":"Computer Architecture - Introduction and Integer Addition","year":"2004","author":"sohn","key":"7"},{"key":"6","article-title":"sis: a system for sequential circuit synthesis","author":"sentovich","year":"1992","journal-title":"Berkeley"},{"key":"5","first-page":"112","article-title":"a new architecture for signed radix 2m pure array multipliers","author":"costa","year":"2002","journal-title":"IEEE International Conference on Computer Design"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-2355-0"},{"journal-title":"Computer Arithmetic - Principles Architecture and Design","year":"1979","author":"hwang","key":"9"},{"key":"8","first-page":"79","article-title":"sls: an efficient switch-level timing simulator using min-max voltage waveforms","author":"genderen","year":"1978","journal-title":"International Conference on Very Large Scale Integration VLSI"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/ARITH.2001.930100"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/4.540066"}],"event":{"name":"2008 2nd International Conference on Signals, Circuits and Systems (SCS)","start":{"date-parts":[[2008,11,7]]},"location":"Nabeul, Tunisia","end":{"date-parts":[[2008,11,9]]}},"container-title":["2008 2nd International Conference on Signals, Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4733847\/4746852\/04746936.pdf?arnumber=4746936","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,17]],"date-time":"2017-03-17T11:54:01Z","timestamp":1489751641000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4746936\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,11]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/icscs.2008.4746936","relation":{},"subject":[],"published":{"date-parts":[[2008,11]]}}}