{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,19]],"date-time":"2025-03-19T11:17:50Z","timestamp":1742383070524,"version":"3.28.0"},"reference-count":18,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/ipdps.2003.1213335","type":"proceedings-article","created":{"date-parts":[[2004,3,22]],"date-time":"2004-03-22T09:34:28Z","timestamp":1079948068000},"page":"8","source":"Crossref","is-referenced-by-count":5,"title":["Loop dissevering: a technique for temporally partitioning loops in dynamically reconfigurable computing platforms"],"prefix":"10.1109","author":[{"given":"J.M.P.","family":"Cardoso","sequence":"first","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/197405.197406"},{"journal-title":"Advanced Compiler Design and Implementation","year":"1997","author":"muchnick","key":"ref11"},{"key":"ref12","first-page":"71","author":"muraoka","year":"1971","journal-title":"Parallelism exposure and exploitation in programs"},{"key":"ref13","doi-asserted-by":"crossref","first-page":"29","DOI":"10.1145\/356683.356686","article-title":"A survey of parallel machine organization and programming","volume":"9","author":"david kuck","year":"1977","journal-title":"ACM Computing Surveys (CSUR)"},{"key":"ref14","article-title":"SUIF: An Infrastructure for Research on Parallelizing and Optimizing Compilers","volume":"29","author":"wilson","year":"1996","journal-title":"ACM SIGPLAN Notices"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/43.908452"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/343647.343789"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-44614-1_73"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/2.839324"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2001.915091"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.1998.707886"},{"key":"ref6","first-page":"616","article-title":"An Automated Temporal Partitioning and Loop Fission approach for FPGA based reconfigurable synthesis of DSP ap plications","author":"kaul","year":"1999","journal-title":"Proc Conference on Design Automation (DAC'99)"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-46117-5_89"},{"journal-title":"The XPP White Paper","year":"2002","key":"ref8"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.2002.1106688"},{"journal-title":"Virtex-II 1 5V Field-Programmable Gate Arrays (v1 7) - Advance Product Specification","year":"2001","key":"ref2"},{"key":"ref1","article-title":"Reconfigurable Architectures for General Purpose Computing","author":"dehon","year":"1996","journal-title":"AI Technical Report 1586"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2003.1253670"}],"event":{"name":"International Parallel and Distributed Processing Symposium (IPDPS 2003)","acronym":"IPDPS-03","location":"Nice, France"},"container-title":["Proceedings International Parallel and Distributed Processing Symposium"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8608\/27277\/01213335.pdf?arnumber=1213335","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,16]],"date-time":"2017-06-16T00:26:04Z","timestamp":1497572764000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1213335\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":18,"URL":"https:\/\/doi.org\/10.1109\/ipdps.2003.1213335","relation":{},"subject":[]}}