{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T07:13:19Z","timestamp":1730272399661,"version":"3.28.0"},"reference-count":16,"publisher":"IEEE","license":[{"start":{"date-parts":[[2008,5,1]],"date-time":"2008-05-01T00:00:00Z","timestamp":1209600000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2008,5,1]],"date-time":"2008-05-01T00:00:00Z","timestamp":1209600000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2008,5]]},"DOI":"10.1109\/iscas.2008.4541394","type":"proceedings-article","created":{"date-parts":[[2008,6,16]],"date-time":"2008-06-16T16:26:17Z","timestamp":1213633577000},"page":"220-223","source":"Crossref","is-referenced-by-count":1,"title":["Power-and-area efficient 14-bit 1.5 MSample\/s two-stage algorithmic ADC based on a mismatch-insensitive MDAC"],"prefix":"10.1109","author":[{"given":"B.","family":"Esperanca","sequence":"first","affiliation":[{"name":"Universidade Nova de Lisboa\/UNINOVA, Campus da FCT\/UNL, 2829 - 517 Caparica - PORTUGAL"}]},{"given":"J.","family":"Goes","sequence":"additional","affiliation":[{"name":"Universidade Nova de Lisboa\/UNINOVA, Campus da FCT\/UNL, 2829 - 517 Caparica - PORTUGAL"}]},{"given":"R.","family":"Tavares","sequence":"additional","affiliation":[{"name":"Universidade Nova de Lisboa\/UNINOVA, Campus da FCT\/UNL, 2829 - 517 Caparica - PORTUGAL"}]},{"given":"A.","family":"Galhardo","sequence":"additional","affiliation":[{"name":"ISEL - DEEA, Av. Em\u00eddio Navarro, n\u00b0 1, 1949 - 014 Lisboa - PORTUGAL"}]},{"given":"N.","family":"Paulino","sequence":"additional","affiliation":[{"name":"Universidade Nova de Lisboa\/UNINOVA, Campus da FCT\/UNL, 2829 - 517 Caparica - PORTUGAL"}]},{"given":"M.","family":"Medeiros Silva","sequence":"additional","affiliation":[{"name":"INESC-ID, Rua Alves Redol, 9, 1000-029 Lisboa - PORTUGAL"}]}],"member":"263","reference":[{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2006.884123"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2006.1693006"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/4.924862"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/82.826750"},{"key":"11","first-page":"1904","article-title":"digital background calibration of a 10-b 40 msample\/s parallel pipelined adc","volume":"33","author":"fu","year":"1998","journal-title":"IEEE J of Solid-State Circuits"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/4.90028"},{"key":"3","first-page":"62","article-title":"a 14 b 20 mw 640 mhz cmos ct sd adc with 20mhz signal bandwidth and 12b enob","author":"mitteregger","year":"2006","journal-title":"Proc IEEE ISSCC"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2002.804330"},{"key":"1","first-page":"96","article-title":"analog technology of all varieties dominate isscc","author":"goodenough","year":"1996","journal-title":"Electronic Design"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/4.261994"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIR.2005.1541585"},{"key":"6","first-page":"76","article-title":"an 80\/100 ms\/s 76.3\/70.1 db sndr adc for digital tv receivers","author":"fujimoto","year":"2006","journal-title":"Proc IEEE ISSCC"},{"key":"5","first-page":"70","article-title":"a 5.4 mw 2-channel time-interleaved multi-bit sd modulator with 80 db snr and 85 db dr for adsl","author":"lee","year":"2006","journal-title":"Proc IEEE ISSCC"},{"key":"4","first-page":"68","article-title":"a 14 mw multi-bit modulator with 82 db snr and 86 db dr for adsl2+, proc","author":"kwon","year":"2006","journal-title":"IEEE ISSCC"},{"key":"9","article-title":"optimum sizing and compensation of two-stage cmos amplifiers based on a time-domain approach","author":"tavares","year":"2006","journal-title":"ICECS'06"},{"key":"8","first-page":"224","article-title":"a 14b 100 ms\/s digitally self-calibrated pipelined adc in 0.13um cmos","author":"bogner","year":"2006","journal-title":"Proc IEEE ISSCC"}],"event":{"name":"2008 IEEE International Symposium on Circuits and Systems (ISCAS)","start":{"date-parts":[[2008,5,18]]},"location":"Seattle, WA, USA","end":{"date-parts":[[2008,5,21]]}},"container-title":["2008 IEEE International Symposium on Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4534149\/4541329\/04541394.pdf?arnumber=4541394","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,2,16]],"date-time":"2024-02-16T01:25:44Z","timestamp":1708046744000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/4541394\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,5]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1109\/iscas.2008.4541394","relation":{},"subject":[],"published":{"date-parts":[[2008,5]]}}}