{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T11:59:19Z","timestamp":1759147159064,"version":"3.28.0"},"reference-count":7,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,6]]},"DOI":"10.1109\/iscas.2014.6865392","type":"proceedings-article","created":{"date-parts":[[2014,7,30]],"date-time":"2014-07-30T21:16:29Z","timestamp":1406754989000},"page":"1344-1347","source":"Crossref","is-referenced-by-count":3,"title":["A low power 4<sup>th<\/sup> order MASH switched-capacitor ΣΔ modulator using ultra incomplete settling"],"prefix":"10.1109","author":[{"given":"Blazej","family":"Nowacki","sequence":"first","affiliation":[]},{"given":"Nuno","family":"Paulino","sequence":"additional","affiliation":[]},{"given":"Joao","family":"Goes","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/4.585244"},{"key":"2","doi-asserted-by":"crossref","first-page":"271","DOI":"10.1109\/ESSCIRC.2011.6044959","article-title":"A 1. 2 v 300 uW second-order switched-capacitor delta sigma modulator using ultra incomplete settling with 73 dB SNDR and 300 kHz BW in 130 nm CMOS","author":"nowacki","year":"2011","journal-title":"European Solid-State Circuits Conference (ESSCIRC)"},{"journal-title":"Understanding Delta-Sigma Data Converters","year":"2005","author":"schreier","key":"1"},{"key":"7","first-page":"36","article-title":"A 32nm, 1. 05V, BIST enabled, 10-40MHz, 11-9 bit, 0. 13mm2 digitized integrator MASH Sigma Delta ADC","author":"carlton","year":"2011","journal-title":"VLSI Circuits (VLSIC) 2011 Symposium on"},{"key":"6","first-page":"164","article-title":"An 85dB SFDR 67dB SNDR 8OSR 240MS\/s SDM ADC with nonlinear memory error calibration","author":"seung-chul","year":"2012","journal-title":"VLSI Circuits (VLSIC) 2012 Symposium on"},{"key":"5","doi-asserted-by":"crossref","first-page":"1614","DOI":"10.1109\/TCSI.2012.2206509","article-title":"A 75-dB SNDR, 5-MHz Bandwidth Stage-Shared 2-2 MASH DS Modulator Dissipating 16 mW Power","volume":"59","author":"zanbaghi","year":"2012","journal-title":"Circuits and Systems I Regular Papers IEEE Transactions on"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/4.210039"}],"event":{"name":"2014 IEEE International Symposium on Circuits and Systems (ISCAS)","start":{"date-parts":[[2014,6,1]]},"location":"Melbourne VIC, Australia","end":{"date-parts":[[2014,6,5]]}},"container-title":["2014 IEEE International Symposium on Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6852006\/6865048\/06865392.pdf?arnumber=6865392","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,22]],"date-time":"2017-06-22T17:37:33Z","timestamp":1498153053000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6865392\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,6]]},"references-count":7,"URL":"https:\/\/doi.org\/10.1109\/iscas.2014.6865392","relation":{},"subject":[],"published":{"date-parts":[[2014,6]]}}}